From patchwork Tue Jun 9 11:31:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roy Spliet X-Patchwork-Id: 482203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9F6140497 for ; Tue, 9 Jun 2015 21:33:49 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z2Hlb-0007Gq-GH; Tue, 09 Jun 2015 11:32:27 +0000 Received: from mail-wi0-f175.google.com ([209.85.212.175]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z2HlI-00071K-1R for linux-mtd@lists.infradead.org; Tue, 09 Jun 2015 11:32:09 +0000 Received: by wibut5 with SMTP id ut5so14753697wib.1 for ; Tue, 09 Jun 2015 04:31:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:to:cc:subject:date:message-id :content-type; bh=K+bPHOCVdW8nAayeGfEKgFBPj4EI1Labw9IQ2yKmib4=; b=ASiArgKQ8DfGfyIGag3EnGM73/iiRlBS0LM6gc0HsBnwgDAAogdbYNsAAzDbTi1NAP W7IDO/vHqN6vEzn1Ype+MZzOOjEoZMQr2cCIImXyvw0SStlypf/Qtz9GtFP1GMVWvQGc hxhkxw9YjOLaBqQq9D90SBn3H6ib8FiuDXKVWKS6jwNw1cX7lFlivwhizEanU0ojO+z2 1Cv+d17W6mpdNRcBIXKDQLz6XVxjtjrDRCefY91+U/NnpZmWjWv88j28P/ibWBolrztk ONNBgYtgblinNWxWCuvlVOz2IiGf5f0KjpebMBLyplGAQ5cLuHrhIBRJP8++sV9Om35v YvpA== X-Gm-Message-State: ALoCoQn2c+1kLpdvV7iAJpZO06kqqRCJKi7cUVsIZBZ3SSFjeTOP1uy2h5U8gQLV5GScLmdwY6ZsYIuCF/l+I5qu2l2pBVFmAonEgDlrlG2OlWCGgujV1NiQ2NrGUz79/lkltDY8Kpw7 MIME-Version: 1.0 X-Received: by 10.180.76.134 with SMTP id k6mr7440471wiw.43.1433849506241; Tue, 09 Jun 2015 04:31:46 -0700 (PDT) Received: from Seven.fritz.box (a83-163-237-212.adsl.xs4all.nl. [83.163.237.212]) by mx.google.com with ESMTPSA id q4sm8954961wju.14.2015.06.09.04.31.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jun 2015 04:31:45 -0700 (PDT) From: Roy Spliet To: Boris Brezillon , Linux MTD , Linux ARM Kernel , Maxime Ripard , Brian Norris , David Woodhouse Subject: [PATCH v2] mtd: nand: Sunxi calculate timing cfg Date: Tue, 9 Jun 2015 13:31:38 +0200 Message-Id: <1433849498-3270-1-git-send-email-r.spliet@ultimaker.com> X-Mailer: git-send-email 2.4.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150609_043208_265653_F82DEC02 X-CRM114-Status: GOOD ( 16.49 ) X-Spam-Score: 0.3 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (0.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.175 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.175 listed in wl.mailspike.net] 1.0 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Roy Spliet X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Values derived from the A83 user manual V2: fix crippled comments Signed-off-by: Roy Spliet --- drivers/mtd/nand/sunxi_nand.c | 42 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index 6f93b29..86de7e3 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -208,6 +208,7 @@ struct sunxi_nand_hw_ecc { * @nand: base NAND chip structure * @mtd: base MTD structure * @clk_rate: clk_rate required for this NAND chip + * @timing_cfg TIMING_CFG register value for this NAND chip * @selected: current active CS * @nsels: number of CS lines required by the NAND chip * @sels: array of CS lines descriptions @@ -217,6 +218,7 @@ struct sunxi_nand_chip { struct nand_chip nand; struct mtd_info mtd; unsigned long clk_rate; + u32 timing_cfg; int selected; int nsels; struct sunxi_nand_chip_sel sels[0]; @@ -403,6 +405,7 @@ static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip) } } + writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG); writel(ctl, nfc->regs + NFC_REG_CTL); sunxi_nand->selected = chip; @@ -807,10 +810,28 @@ static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd, return 0; } +static const s32 tWB_lut[] = {6, 12, 16, 20, -1}; +static const s32 tRHW_lut[] = {4, 8, 12, 20, -1}; + +static s32 sunxi_nand_lookup_timing(const s32 *lut, u32 period, u32 clk_period) +{ + u32 clks = (period + clk_period - 1) / clk_period; + int i; + + for (i = 0; lut[i] != -1; i++) { + if (clks <= lut[i]) + return i; + } + + /* Return max value */ + return i - 1; +} + static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, const struct nand_sdr_timings *timings) { u32 min_clk_period = 0; + u32 tWB, tADL, tWHR, tRHW, tCAD; /* T1 <=> tCLS */ if (timings->tCLS_min > min_clk_period) @@ -872,6 +893,20 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, if (timings->tWC_min > (min_clk_period * 2)) min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); + /* T16 - T19 + tCAD */ + tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, + min_clk_period); + tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; + tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; + tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, + min_clk_period); + tCAD = 0x7; + chip->timing_cfg = (tWB & 0x3) | + (tADL & 0x3) << 2 | + (tWHR & 0x3) << 4 | + (tRHW & 0x3) << 6 | + (tCAD & 0x7) << 8; + /* \todo A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ /* Convert min_clk_period from picoseconds to nanoseconds */ min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); @@ -884,8 +919,6 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, */ chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period; - /* TODO: configure T16-T19 */ - return 0; } @@ -1168,6 +1201,7 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc, chip->nsels = nsels; chip->selected = -1; + chip->timing_cfg = 0x7ff; for (i = 0; i < nsels; i++) { ret = of_property_read_u32_index(np, "reg", i, &tmp); @@ -1377,11 +1411,9 @@ static int sunxi_nfc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, nfc); /* - * TODO: replace these magic values with proper flags as soon as we - * know what they are encoding. + * TODO: replace this magic values with EDO flag */ writel(0x100, nfc->regs + NFC_REG_TIMING_CTL); - writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG); ret = sunxi_nand_chips_init(dev, nfc); if (ret) {