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[1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

Message ID 1425643938-24749-2-git-send-email-rnd4@dave-tech.it
State Changes Requested
Headers show

Commit Message

rnd4@dave-tech.it March 6, 2015, 12:12 p.m. UTC 
From: Andrea Scian <andrea.scian@dave.eu>

MLC NANDs have more bit flips that SLC. When looking for bad block
marker we have a lot of false positive if we check for the whole byte. To
avoid this tolerate a few (4 here) bit flips for byte.

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
---
 drivers/mtd/nand/nand_base.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Boris Brezillon March 15, 2015, 9:07 a.m. UTC | #1 
Hi Andrea,

On Fri,  6 Mar 2015 13:12:17 +0100
rnd4@dave-tech.it wrote:

> From: Andrea Scian <andrea.scian@dave.eu>
> 
> MLC NANDs have more bit flips that SLC. When looking for bad block
> marker we have a lot of false positive if we check for the whole byte. To
> avoid this tolerate a few (4 here) bit flips for byte.

I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
this value should be chip dependent.
I know there is currently no way to retrieve this information, so here
are two suggestions:

1/ make this value depend on the required NAND ecc strength
(badblockbits = ecc_strength / 10 ?)
2/ let each controller change this value after nand_scan_ident
depending on the detected chip until we find a generic solution to
select this value

Best Regards,

Boris
rnd4@dave-tech.it April 3, 2015, 12:52 p.m. UTC | #2 
Sorry for the later feedback, but unfortunately I had to move to other
stuff before coming back to this topic

Il 15/03/2015 10:07, Boris Brezillon ha scritto:
> Hi Andrea,
> 
> On Fri,  6 Mar 2015 13:12:17 +0100
> rnd4@dave-tech.it wrote:
> 
>> From: Andrea Scian <andrea.scian@dave.eu>
>>
>> MLC NANDs have more bit flips that SLC. When looking for bad block
>> marker we have a lot of false positive if we check for the whole byte. To
>> avoid this tolerate a few (4 here) bit flips for byte.
> 
> I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
> this value should be chip dependent.

I agree

> I know there is currently no way to retrieve this information,

For this reason I just put a hardcoded value.

> so here are two suggestions:
> 
> 1/ make this value depend on the required NAND ecc strength
> (badblockbits = ecc_strength / 10 ?)
> 2/ let each controller change this value after nand_scan_ident
> depending on the detected chip until we find a generic solution to
> select this value

I'll try to figure out how to solve this
Any suggestion is welcome!

Regards,
rnd4@dave-tech.it July 23, 2015, 9:24 p.m. UTC | #3 
Dear Bean,

Il 21/07/2015 16:50, Bean Huo 霍斌斌 (beanhuo) ha scritto:
 > Hi,
 > What is status of this patch? I think 4 bits is make sense for all
 > MLC nand,
 > Bit flips on bad block mark should not be regarded as a bad block.
 >

I think that there was something wrong with your email, because I didn't 
see it in MTD ML archives, probably it has been blocked for some reason.

I didn't find a solution to implement Boris suggestions on how to choose 
the bad block bit threshold. In my implementation is still statically 
defined.

However I did some minor changes to the second patch, I'll send it in a 
few minutes.

Any feedback is welcome, of course ;-)

Kind Regards,

Andrea Scian


Il 03/04/2015 14:52, Andrea Scian ha scritto:
>
> Sorry for the later feedback, but unfortunately I had to move to other
> stuff before coming back to this topic
>
> Il 15/03/2015 10:07, Boris Brezillon ha scritto:
>> Hi Andrea,
>>
>> On Fri,  6 Mar 2015 13:12:17 +0100
>> rnd4@dave-tech.it wrote:
>>
>>> From: Andrea Scian <andrea.scian@dave.eu>
>>>
>>> MLC NANDs have more bit flips that SLC. When looking for bad block
>>> marker we have a lot of false positive if we check for the whole byte. To
>>> avoid this tolerate a few (4 here) bit flips for byte.
>>
>> I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
>> this value should be chip dependent.
>
> I agree
>
>> I know there is currently no way to retrieve this information,
>
> For this reason I just put a hardcoded value.
>
>> so here are two suggestions:
>>
>> 1/ make this value depend on the required NAND ecc strength
>> (badblockbits = ecc_strength / 10 ?)
>> 2/ let each controller change this value after nand_scan_ident
>> depending on the detected chip until we find a generic solution to
>> select this value
>
> I'll try to figure out how to solve this
> Any suggestion is welcome!
>
> Regards,
>
Brian Norris July 23, 2015, 10 p.m. UTC | #4 
On Thu, Jul 23, 2015 at 11:24:54PM +0200, Andrea Scian wrote:
> Il 21/07/2015 16:50, Bean Huo 霍斌斌 (beanhuo) ha scritto:
> > Hi,
> > What is status of this patch? I think 4 bits is make sense for all
> > MLC nand,
> > Bit flips on bad block mark should not be regarded as a bad block.
> >
> 
> I think that there was something wrong with your email, because I
> didn't see it in MTD ML archives, probably it has been blocked for
> some reason.

X-Bad-Reply: 'Re:' in Subject but no References or In-Reply-To headers

I would let it through the moderation filter, but it would screw with
everybody's threading, and the entire contents are there in the quote
anyway.

Bean: please fix your mailer.

Regards,
Brian
diff mbox

Patch

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dfcd0a5..bdca223 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3315,7 +3315,10 @@  ident_done:
 		chip->chip_shift += 32 - 1;
 	}
 
-	chip->badblockbits = 8;
+	if (nand_is_slc(chip))
+		chip->badblockbits = 8;
+	else
+		chip->badblockbits = 4;
 	chip->erase_cmd = single_erase_cmd;
 
 	/* Do not replace user supplied command function! */