From patchwork Thu Jan 23 10:31:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 313509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E3C952C0092 for ; Thu, 23 Jan 2014 22:03:39 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6I3b-0008Nw-7v; Thu, 23 Jan 2014 11:02:48 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6I38-0004lp-5w; Thu, 23 Jan 2014 11:02:18 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6I2X-0004dX-Nw for linux-mtd@merlin.infradead.org; Thu, 23 Jan 2014 11:01:41 +0000 Received: from mail-wi0-f171.google.com ([209.85.212.171]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6HbP-00081O-0o for linux-mtd@lists.infradead.org; Thu, 23 Jan 2014 10:33:40 +0000 Received: by mail-wi0-f171.google.com with SMTP id cc10so6622713wib.16 for ; Thu, 23 Jan 2014 02:33:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VjSY1719DEYYz78/Qab4ZUdcPv1Xe3jM8Ga5CqFLKD0=; b=U8EC2cXterCChUBxgmhIODK1tGZvigyCliQaraDTxORCO59RU+FJqCyCS3MoAX4pYC 2LFZ0/6UjztuWO0Qk8KO8Yzpv1i9OAwUmTTh20a62/81pUwMsMTCY/0aNOL34QFV/dVX vutgLpYw9pYHtlg5fZ4//IbCcnviQIuBtyclmKJay5NE1ITvu7or2a4o7jFit+KgF9y1 JldOS3dX9HOXdWE8j1wlpvOo40tavPtAeSPBVgHvv7Zqb68ZMJJNaLbO6UDtUrERVWe3 xC8/gfK33F4M+QEAFRR1tP3dmNmld113eQtfuh0kEvrSYBO5kgOcSVtqwp2yRW8j1mnB YAsQ== X-Gm-Message-State: ALoCoQl3oKb2Z9stccBi/2PDzOEg3c7etqYzBsuftNR9yD/Jl5iTVUCv79a1mbpDoaHH4kQzEeGb X-Received: by 10.195.12.164 with SMTP id er4mr390145wjd.92.1390473196698; Thu, 23 Jan 2014 02:33:16 -0800 (PST) Received: from localhost.localdomain ([80.76.198.141]) by mx.google.com with ESMTPSA id ay6sm21257831wjb.23.2014.01.23.02.33.13 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Jan 2014 02:33:15 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v4 36/37] mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct Date: Thu, 23 Jan 2014 10:31:24 +0000 Message-Id: <1390473085-24626-37-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> References: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140123_023339_375680_DE44F525 X-CRM114-Status: GOOD ( 12.68 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.171 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record Cc: olivier.clergeaud@st.com, Angus.Clark@st.com, Lee Jones , linus.walleij@linaro.org, linux-mtd@lists.infradead.org, computersforpeace@gmail.com, dwmw2@infradead.org, DCG_UPD_stlinux_kernel@list.st.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 64 ++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index ddfff35..541e867 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -271,6 +271,19 @@ #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 +struct stfsm_seq { + uint32_t data_size; + uint32_t addr1; + uint32_t addr2; + uint32_t addr_cfg; + uint32_t seq_opc[5]; + uint32_t mode; + uint32_t dummy; + uint32_t status; + uint8_t seq[16]; + uint32_t seq_cfg; +} __packed __aligned(4); + struct stfsm { struct device *dev; void __iomem *base; @@ -284,20 +297,11 @@ struct stfsm { bool booted_from_spi; bool reset_signal; bool reset_por; -}; -struct stfsm_seq { - uint32_t data_size; - uint32_t addr1; - uint32_t addr2; - uint32_t addr_cfg; - uint32_t seq_opc[5]; - uint32_t mode; - uint32_t dummy; - uint32_t status; - uint8_t seq[16]; - uint32_t seq_cfg; -} __packed __aligned(4); + struct stfsm_seq stfsm_seq_read; + struct stfsm_seq stfsm_seq_write; + struct stfsm_seq stfsm_seq_en_32bit_addr; +}; /* Parameters to configure a READ or WRITE FSM sequence */ struct seq_rw_config { @@ -585,10 +589,6 @@ static struct seq_rw_config stfsm_s25fl_write4_configs[] = { */ #define W25Q_STATUS_QE (0x1 << 9) -static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ -static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ -static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ - static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -819,7 +819,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { - struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr; + struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -1091,7 +1091,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) int ret; /* Configure 'READ' sequence */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, default_read_configs); if (ret) { dev_err(fsm->dev, @@ -1101,7 +1101,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) } /* Configure 'WRITE' sequence */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, default_write_configs); if (ret) { dev_err(fsm->dev, @@ -1136,7 +1136,7 @@ static int stfsm_mx25_config(struct stfsm *fsm) */ if (flags & FLASH_FLAG_32BIT_ADDR) { /* Configure 'enter_32bitaddr' FSM sequence */ - stfsm_mx25_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); soc_reset = stfsm_can_handle_soc_reset(fsm); if (soc_reset || !fsm->booted_from_spi) { @@ -1159,7 +1159,7 @@ static int stfsm_mx25_config(struct stfsm *fsm) } /* For QUAD mode, set 'QE' STATUS bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta); sta |= MX25_STATUS_QE; @@ -1178,10 +1178,10 @@ static int stfsm_n25q_config(struct stfsm *fsm) /* Configure 'READ' sequence */ if (flags & FLASH_FLAG_32BIT_ADDR) - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, n25q_read4_configs); else - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, n25q_read3_configs); if (ret) { dev_err(fsm->dev, @@ -1191,7 +1191,7 @@ static int stfsm_n25q_config(struct stfsm *fsm) } /* Configure 'WRITE' sequence (default configs) */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, default_write_configs); if (ret) { dev_err(fsm->dev, @@ -1205,7 +1205,7 @@ static int stfsm_n25q_config(struct stfsm *fsm) /* Configure 32-bit address support */ if (flags & FLASH_FLAG_32BIT_ADDR) { - stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); soc_reset = stfsm_can_handle_soc_reset(fsm); if (soc_reset || !fsm->booted_from_spi) { @@ -1364,12 +1364,12 @@ static int stfsm_s25fl_config(struct stfsm *fsm) * Prepare Read/Write/Erase sequences according to S25FLxxx * 32-bit address command set */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, stfsm_s25fl_read4_configs); if (ret) return ret; - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, stfsm_s25fl_write4_configs); if (ret) return ret; @@ -1405,7 +1405,7 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } /* Check status of 'QE' bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1); if (data_pads == 4) { if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { @@ -1455,7 +1455,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) return ret; /* If using QUAD mode, set QE STATUS bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta1); stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sta2); @@ -1475,7 +1475,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, uint32_t offset) { - struct stfsm_seq *seq = &stfsm_seq_read; + struct stfsm_seq *seq = &fsm->stfsm_seq_read; uint32_t data_pads; uint32_t read_mask; uint32_t size_ub; @@ -1536,7 +1536,7 @@ static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, static int stfsm_write(struct stfsm *fsm, const uint8_t *const buf, const uint32_t size, const uint32_t offset) { - struct stfsm_seq *seq = &stfsm_seq_write; + struct stfsm_seq *seq = &fsm->stfsm_seq_write; uint32_t data_pads; uint32_t write_mask; uint32_t size_ub;