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Thu, 23 Jan 2014 02:33:03 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v4 32/37] mtd: st_spi_fsm: Add the ability to write to FSM's status register Date: Thu, 23 Jan 2014 10:31:20 +0000 Message-Id: <1390473085-24626-33-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> References: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140123_053326_663501_7D768880 X-CRM114-Status: GOOD ( 11.40 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.170 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: olivier.clergeaud@st.com, Angus.Clark@st.com, Lee Jones , linus.walleij@linaro.org, linux-mtd@lists.infradead.org, computersforpeace@gmail.com, dwmw2@infradead.org, DCG_UPD_stlinux_kernel@list.st.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 5f291dc..1b0fa67 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -586,6 +586,23 @@ static struct stfsm_seq stfsm_seq_erase_chip = { SEQ_CFG_STARTSEQ), }; +static struct stfsm_seq stfsm_seq_write_status = { + .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WRSR)), + .seq = { + STFSM_INST_CMD1, + STFSM_INST_CMD2, + STFSM_INST_STA_WR1, + STFSM_INST_STOP, + }, + .seq_cfg = (SEQ_CFG_PADS_1 | + SEQ_CFG_READNOTWRITE | + SEQ_CFG_CSDEASSERT | + SEQ_CFG_STARTSEQ), +}; + static struct stfsm_seq stfsm_seq_wrvcr = { .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), @@ -802,6 +819,25 @@ static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd, return 0; } +static int stfsm_write_status(struct stfsm *fsm, uint16_t status, + int sta_bytes) +{ + struct stfsm_seq *seq = &stfsm_seq_write_status; + + dev_dbg(fsm->dev, "writing STA[%s] 0x%04x\n", + (sta_bytes == 1) ? "1" : "1+2", status); + + seq->status = (uint32_t)status | STA_PADS_1 | STA_CSDEASSERT; + seq->seq[2] = (sta_bytes == 1) ? + STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2; + + stfsm_load_seq(fsm, seq); + + stfsm_wait_seq(fsm); + + return 0; +}; + static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data) { struct stfsm_seq *seq = &stfsm_seq_wrvcr;