From patchwork Thu Jan 23 10:31:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 313585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CF1A52C0091 for ; Thu, 23 Jan 2014 23:29:44 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6HeH-0007pa-Or; Thu, 23 Jan 2014 10:36:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6Hdf-0003TT-HW; Thu, 23 Jan 2014 10:35:59 +0000 Received: from mail-we0-f172.google.com ([74.125.82.172]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W6Haf-00033Q-S5 for linux-mtd@lists.infradead.org; Thu, 23 Jan 2014 10:33:02 +0000 Received: by mail-we0-f172.google.com with SMTP id q58so956517wes.31 for ; Thu, 23 Jan 2014 02:32:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fBxR1FdsctnsbcHUGhf4YluRzwq5yaB6KgmykjcA8bk=; b=b0p4MOaB2QVOk1NpprVrUdxYLvjYgn+EBvBaUq1rgL8kbvhdwI16Duku/RXsyT1dfv b7MXEURgvYFeOSbxcqBH/GEQRhEp+3qswoeiM9YQirqXX42QVs1GW7QgZLmrZNO4NMDp Gw4XbyvejYydJDRwmecuSVTNUdrHZxXnYKWqxGXoQN1cVl0HWUDYy6XV5uU/BlXXNbeZ yPl2Xqs+Mb/VQxTGftOS0zZVO7WulnKzp8RiLZCwNUcrAU+HRx+PFzl3mO1G2mpeJs54 OK1EoK3mPC1AUJfhhUICIKdNkK+n3meQ+IWUXDMKfX/yggxxrWyrf9NuQLppso5/oG/Z T33Q== X-Gm-Message-State: ALoCoQlpNduAJVybHThRXKeonapx/kgPwkuqNXZtnERfZjwLxoNNM4ph0N/3STgx2bnpCDGSbF4y X-Received: by 10.180.19.35 with SMTP id b3mr24034184wie.20.1390473151586; Thu, 23 Jan 2014 02:32:31 -0800 (PST) Received: from localhost.localdomain ([80.76.198.141]) by mx.google.com with ESMTPSA id ay6sm21257831wjb.23.2014.01.23.02.32.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Jan 2014 02:32:30 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v4 20/37] mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing mode Date: Thu, 23 Jan 2014 10:31:08 +0000 Message-Id: <1390473085-24626-21-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> References: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140123_053254_308912_97F456E4 X-CRM114-Status: GOOD ( 12.32 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: olivier.clergeaud@st.com, Angus.Clark@st.com, Lee Jones , linus.walleij@linaro.org, linux-mtd@lists.infradead.org, computersforpeace@gmail.com, dwmw2@infradead.org, DCG_UPD_stlinux_kernel@list.st.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index b21929b..e74513d 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -411,6 +411,8 @@ static struct flash_info flash_types[] = { { NULL, 0x000000, 0, 0, 0, 0, 0, NULL }, }; +static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ + static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -554,6 +556,23 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, } } +static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) +{ + struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr; + uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; + + seq->seq_opc[0] = (SEQ_OPC_PADS_1 | + SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(cmd) | + SEQ_OPC_CSDEASSERT); + + stfsm_load_seq(fsm, seq); + + stfsm_wait_seq(fsm); + + return 0; +} + /* * SoC reset on 'boot-from-spi' systems *