From patchwork Fri Nov 22 16:22:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 293532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0085D2C00F9 for ; Sat, 23 Nov 2013 03:43:38 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vjtou-00048j-KG; Fri, 22 Nov 2013 16:43:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vjtoi-0003yD-C4; Fri, 22 Nov 2013 16:42:52 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjtoG-0003t8-8k for linux-mtd@merlin.infradead.org; Fri, 22 Nov 2013 16:42:24 +0000 Received: from mail-pb0-f43.google.com ([209.85.160.43]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjtX6-00057P-PU for linux-mtd@lists.infradead.org; Fri, 22 Nov 2013 16:24:41 +0000 Received: by mail-pb0-f43.google.com with SMTP id rq2so1502661pbb.16 for ; Fri, 22 Nov 2013 08:24:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I4mnMxekS1GFLWv3ezsVrZS+ZHVciT7M/Hmn2SoIiog=; b=Y4l4ovDXDBEDTKICTBvnmu56sXAw9y2IAiQvmuGh3YsriUPTAzqqy4stEpYAFoteC3 P7DBhdbKs8GwlYxajAUXk52apA5EH0ny4cGtFli5x32+LRcGYQfUr7omAT8Nyx7mesSE TSz2tbgr3VGwRYGsXR/x/jQ2ce/OkyLVjry2O89sRoXliFXpzV/M7gOGhDVjk/QlPd6v uzFzGW0S5yQxNwOiGIrhHgMgbes/h/BpWk4WTPM6BhrTePQ864iyv0K+A6SYAOGktZVZ C7bo1TzEykFyOwvzV25Xv2s0CBdNfcXEGYPvU3zV2zCUbLmPAH/clx5eecuHoHxOXJ2X CNlQ== X-Gm-Message-State: ALoCoQkijv35EQLZ3u6Z2wk3WSAfZvgyfOWIRvjpsk3qvapQM2KNnl3l1jW17nYpOhwbcO6OdIwI X-Received: by 10.66.144.40 with SMTP id sj8mr12985950pab.4.1385137454567; Fri, 22 Nov 2013 08:24:14 -0800 (PST) Received: from localhost.localdomain (cpc15-aztw25-2-0-cust493.aztw.cable.virginm.net. [92.233.57.238]) by mx.google.com with ESMTPSA id qz9sm52962938pbc.3.2013.11.22.08.24.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 22 Nov 2013 08:24:13 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dwmw2@infradead.org, linux-mtd@lists.infradead.org, angus.clark@st.com Subject: [PATCH 19/23] mtd: st_spi_fsm: Add a check to if the chip can handle an SoC reset Date: Fri, 22 Nov 2013 16:22:56 +0000 Message-Id: <1385137380-28968-20-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1385137380-28968-1-git-send-email-lee.jones@linaro.org> References: <1385137380-28968-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131122_162440_998381_A923B78E X-CRM114-Status: GOOD ( 20.12 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-2.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.43 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linus.walleij@linaro.org, Lee Jones X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 38 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/devices/st_spi_fsm.h | 2 ++ 2 files changed, 40 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 85abf9a..9a66c99 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -128,6 +128,40 @@ static void stfsm_wait_seq(struct stfsm *fsm) dev_err(fsm->dev, "timeout on sequence completion\n"); } +/* + * SoC reset on 'boot-from-spi' systems + * + * Certain modes of operation cause the Flash device to enter a particular state + * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit + * Addr' commands). On boot-from-spi systems, it is important to consider what + * happens if a warm reset occurs during this period. The SPIBoot controller + * assumes that Flash device is in its default reset state, 24-bit address mode, + * and ready to accept commands. This can be achieved using some form of + * on-board logic/controller to force a device POR in response to a SoC-level + * reset or by making use of the device reset signal if available (limited + * number of devices only). + * + * Failure to take such precautions can cause problems following a warm reset. + * For some operations (e.g. ERASE), there is little that can be done. For + * other modes of operation (e.g. 32-bit addressing), options are often + * available that can help minimise the window in which a reset could cause a + * problem. + * + */ +static bool stfsm_can_handle_soc_reset(struct stfsm *fsm) +{ + /* Reset signal is available on the board and supported by the device */ + if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET) + return true; + + /* Board-level logic forces a power-on-reset */ + if (fsm->reset_por) + return true; + + /* Reset is not properly handled and may result in failure to reboot */ + return false; +} + /* Configure 'addr_cfg' according to addressing mode */ static void stfsm_prepare_erasesec_seq(struct stfsm *fsm, struct stfsm_seq *seq) @@ -442,6 +476,10 @@ static void stfsm_fetch_platform_configs(struct platform_device *pdev) goto boot_device_fail; } + fsm->reset_signal = of_property_read_bool(np, "st,reset-signal"); + + fsm->reset_por = of_property_read_bool(np, "st,reset-por"); + /* Where in the syscon the boot device information lives */ ret = of_property_read_u32(np, "boot-device-reg", &boot_device_reg); if (ret) diff --git a/drivers/mtd/devices/st_spi_fsm.h b/drivers/mtd/devices/st_spi_fsm.h index 2e12bff..8eb9e20 100644 --- a/drivers/mtd/devices/st_spi_fsm.h +++ b/drivers/mtd/devices/st_spi_fsm.h @@ -239,6 +239,8 @@ struct stfsm { uint32_t fifo_dir_delay; bool booted_from_spi; + bool reset_signal; + bool reset_por; }; struct stfsm_seq {