From patchwork Fri Jun 29 03:52:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 167909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E64BBB6FBA for ; Fri, 29 Jun 2012 01:49:51 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SkGxU-00017O-Do; Thu, 28 Jun 2012 15:48:40 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SkGwr-0000pr-Fw; Thu, 28 Jun 2012 15:48:02 +0000 Received: by pbbrq13 with SMTP id rq13so3510547pbb.36 for ; Thu, 28 Jun 2012 08:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7snEeG5qCVlqZV2/KFmjbMU58SxxzGanoCB1l/NkQV0=; b=zKYKt3nqKCTC1OSqkxkqxR9YpLFvFPisjb9mvxy5HEzcWzVu2WIQU3OsX4aW5sIWT3 BTPQW2Elxsdn6l4zGKb+Mdw+6UirKxP0Ojg6e0DnwmyB8hJmMTZva2bkomRwlJoqgPGj waFrRaqh8OBIlSqZnFVXhXCDwg263QyzEJmW6kOy6X6RnbwTjNoek08i37jWN8WCym7c 3Eidyui5Cq/zj84UQwWsn/XTVNaOBrMZa/o05mJCF+BpVNmL0V4cHSxgwE4S4Eot/C9U dvv1c2H1RuyBUuL7HY6L0KESd/QIfzt8lnztZEwChApGkOR2JZnSK/NmI11wFuGDkNcL hjqw== Received: by 10.68.221.106 with SMTP id qd10mr9266552pbc.42.1340898479662; Thu, 28 Jun 2012 08:47:59 -0700 (PDT) Received: from localhost.localdomain.Home ([218.81.181.29]) by mx.google.com with ESMTPS id os9sm2441689pbb.62.2012.06.28.08.47.55 (version=SSLv3 cipher=OTHER); Thu, 28 Jun 2012 08:47:59 -0700 (PDT) From: Huang Shijie To: shawn.guo@linaro.org Subject: [PATCH 2/3] ARM: imx6q: add DT node for gpmi nand Date: Thu, 28 Jun 2012 23:52:04 -0400 Message-Id: <1340941925-14591-2-git-send-email-shijie8@gmail.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1340941925-14591-1-git-send-email-shijie8@gmail.com> References: <1340941925-14591-1-git-send-email-shijie8@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: 0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shijie8[at]gmail.com) -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.49 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 3.2 DATE_IN_FUTURE_12_24 Date: is 12 to 24 hours after Received: date 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (shijie8[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Huang Shijie , Huang Shijie , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dedekind1@gmail.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add the DT node for gpmi nand. Add the pinmux support for gpmi nand. The gpmi nand may conflicts with other modules, such as MMC. So we do not enable the gpmi nand for mx6q-arm2 board, just add the node for the board. Signed-off-by: Huang Shijie Signed-off-by: Huang Shijie Acked-by: Dong Aisheng --- arch/arm/boot/dts/imx6q-arm2.dts | 6 ++++++ arch/arm/boot/dts/imx6q.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index bdab44c..d93a2d9 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -22,6 +22,12 @@ }; soc { + gpmi-nand@00112000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 3197744..16a3884 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -92,6 +92,18 @@ reg = <0x00110000 0x2000>; }; + gpmi-nand@00112000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -500,6 +512,30 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + }; + }; + i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */