From patchwork Thu Sep 9 10:20:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zang Roy-R61911 X-Patchwork-Id: 64280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 856C4B6EF7 for ; Thu, 9 Sep 2010 20:44:15 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OteaQ-0005qS-CZ; Thu, 09 Sep 2010 10:42:34 +0000 Received: from am1ehsobe004.messaging.microsoft.com ([213.199.154.207] helo=AM1EHSOBE004.bigfish.com) by bombadil.infradead.org with esmtps (Exim 4.72 #1 (Red Hat Linux)) id 1OteaN-0005i5-1P for linux-mtd@lists.infradead.org; Thu, 09 Sep 2010 10:42:32 +0000 Received: from mail63-am1-R.bigfish.com (10.3.201.247) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 8.1.240.5; Thu, 9 Sep 2010 10:42:25 +0000 Received: from mail63-am1 (localhost.localdomain [127.0.0.1]) by mail63-am1-R.bigfish.com (Postfix) with ESMTP id 010DE978276; Thu, 9 Sep 2010 10:42:26 +0000 (UTC) X-SpamScore: 10 X-BigFish: VS10(zzc8kzz1202hzz8275bhz2dh2a8h68o) X-Spam-TCS-SCL: 7:0 Received: from mail63-am1 (localhost.localdomain [127.0.0.1]) by mail63-am1 (MessageSwitch) id 1284028944487968_6520; Thu, 9 Sep 2010 10:42:24 +0000 (UTC) Received: from am1ehsmhs002.bigfish.com (unknown [10.3.201.241]) by mail63-am1.bigfish.com (Postfix) with ESMTP id 73CAA117004D; Thu, 9 Sep 2010 10:42:24 +0000 (UTC) Received: from az33egw02.freescale.net (192.88.158.103) by am1ehsmhs002.bigfish.com (10.3.207.102) with Microsoft SMTP Server (TLS) id 14.0.482.44; Thu, 9 Sep 2010 10:42:23 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id o89Ag1RV003287; Thu, 9 Sep 2010 03:42:11 -0700 (MST) Received: from localhost.localdomain (rock.ap.freescale.net [10.193.20.106]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id o89AsLLd009206; Thu, 9 Sep 2010 05:54:22 -0500 (CDT) From: Roy Zang To: linux-mtd@lists.infradead.org Subject: [PATCH 1/3 v2][MTD] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices Date: Thu, 9 Sep 2010 18:20:30 +0800 Message-ID: <1284027632-32573-1-git-send-email-tie-fei.zang@freescale.com> X-Mailer: git-send-email 1.5.6.5 MIME-Version: 1.0 X-Reverse-DNS: az33egw02.freescale.net X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100909_064231_332669_C83177A9 X-CRM114-Status: GOOD ( 31.06 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.207 listed in list.dnswl.org] Cc: B07421@freescale.com, dedekind1@gmail.com, B25806@freescale.com, linuxppc-dev@ozlabs.org, cbouatmailru@gmail.com, akpm@linux-foundation.org, dwmw2@infradead.org, B11780@freescale.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Lan Chunhe-B25806 Move Freescale elbc interrupt from nand dirver to elbc driver. Then all elbc devices can use the interrupt instead of ONLY nand. Signed-off-by: Lan Chunhe-B25806 Signed-off-by: Roy Zang --- Comparing with v1, according to the feedback, add some decorations. arch/powerpc/Kconfig | 7 +- arch/powerpc/include/asm/fsl_lbc.h | 34 +++++- arch/powerpc/sysdev/fsl_lbc.c | 248 ++++++++++++++++++++++++++++++------ 3 files changed, 247 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 631e5a0..44df1ba 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -687,9 +687,12 @@ config 4xx_SOC bool config FSL_LBC - bool + bool "Freescale Local Bus support" + depends on FSL_SOC help - Freescale Localbus support + Enables reporting of errors from the Freescale local bus + controller. Also contains some common code used by + drivers for specific local bus peripherals. config FSL_GTM bool diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 1b5a210..9b95eab 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -1,9 +1,10 @@ /* Freescale Local Bus Controller * - * Copyright (c) 2006-2007 Freescale Semiconductor + * Copyright (c) 2006-2007, 2010 Freescale Semiconductor * * Authors: Nick Spence , * Scott Wood + * Jack Lan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,6 +28,9 @@ #include #include +#include +#include + struct fsl_lbc_bank { __be32 br; /**< Base Register */ #define BR_BA 0xFFFF8000 @@ -125,13 +129,23 @@ struct fsl_lbc_regs { #define LTESR_ATMW 0x00800000 #define LTESR_ATMR 0x00400000 #define LTESR_CS 0x00080000 +#define LTESR_UPM 0x00000002 #define LTESR_CC 0x00000001 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) +#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \ + | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \ + | LTESR_CC) +#define LTESR_CLEAR 0xFFFFFFFF +#define LTECCR_CLEAR 0xFFFFFFFF +#define LTESR_STATUS LTESR_MASK +#define LTEIR_ENABLE LTESR_MASK +#define LTEDR_ENABLE 0x00000000 __be32 ltedr; /**< Transfer Error Disable Register */ __be32 lteir; /**< Transfer Error Interrupt Register */ __be32 lteatr; /**< Transfer Error Attributes Register */ __be32 ltear; /**< Transfer Error Address Register */ - u8 res6[0xC]; + __be32 lteccr; /**< Transfer Error ECC Register */ + u8 res6[0x8]; __be32 lbcr; /**< Configuration Register */ #define LBCR_LDIS 0x80000000 #define LBCR_LDIS_SHIFT 31 @@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm) cpu_relax(); } +/* overview of the fsl lbc controller */ + +struct fsl_lbc_ctrl { + /* device info */ + struct device *dev; + struct fsl_lbc_regs __iomem *regs; + int irq; + wait_queue_head_t irq_wait; + spinlock_t lock; + void *nand; + + /* status read from LTESR by irq handler */ + unsigned int irq_status; +}; + extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar); +extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev; #endif /* __ASM_FSL_LBC_H */ diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c index dceb8d1..f4eca8d 100644 --- a/arch/powerpc/sysdev/fsl_lbc.c +++ b/arch/powerpc/sysdev/fsl_lbc.c @@ -2,8 +2,11 @@ * Freescale LBC and UPM routines. * * Copyright (c) 2007-2008 MontaVista Software, Inc. + * Copyright (c) 2010 Freescale Semiconductor * * Author: Anton Vorontsov + * Author: Jack Lan + * Author: Roy Zang * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,37 +24,11 @@ #include #include #include +#include static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock); -static struct fsl_lbc_regs __iomem *fsl_lbc_regs; - -static char __initdata *compat_lbc[] = { - "fsl,pq2-localbus", - "fsl,pq2pro-localbus", - "fsl,pq3-localbus", - "fsl,elbc", -}; - -static int __init fsl_lbc_init(void) -{ - struct device_node *lbus; - int i; - - for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) { - lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]); - if (lbus) - goto found; - } - return -ENODEV; - -found: - fsl_lbc_regs = of_iomap(lbus, 0); - of_node_put(lbus); - if (!fsl_lbc_regs) - return -ENOMEM; - return 0; -} -arch_initcall(fsl_lbc_init); +struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev; +EXPORT_SYMBOL(fsl_lbc_ctrl_dev); /** * fsl_lbc_find - find Localbus bank @@ -65,13 +42,15 @@ arch_initcall(fsl_lbc_init); int fsl_lbc_find(phys_addr_t addr_base) { int i; + struct fsl_lbc_regs __iomem *lbc; - if (!fsl_lbc_regs) + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) return -ENODEV; - for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) { - __be32 br = in_be32(&fsl_lbc_regs->bank[i].br); - __be32 or = in_be32(&fsl_lbc_regs->bank[i].or); + lbc = fsl_lbc_ctrl_dev->regs; + for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { + __be32 br = in_be32(&lbc->bank[i].br); + __be32 or = in_be32(&lbc->bank[i].or); if (br & BR_V && (br & or & BR_BA) == addr_base) return i; @@ -94,22 +73,26 @@ int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm) { int bank; __be32 br; + struct fsl_lbc_regs __iomem *lbc; bank = fsl_lbc_find(addr_base); if (bank < 0) return bank; - br = in_be32(&fsl_lbc_regs->bank[bank].br); + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) + return -ENODEV; + lbc = fsl_lbc_ctrl_dev->regs; + br = in_be32(&lbc->bank[bank].br); switch (br & BR_MSEL) { case BR_MS_UPMA: - upm->mxmr = &fsl_lbc_regs->mamr; + upm->mxmr = &lbc->mamr; break; case BR_MS_UPMB: - upm->mxmr = &fsl_lbc_regs->mbmr; + upm->mxmr = &lbc->mbmr; break; case BR_MS_UPMC: - upm->mxmr = &fsl_lbc_regs->mcmr; + upm->mxmr = &lbc->mcmr; break; default: return -EINVAL; @@ -143,14 +126,18 @@ EXPORT_SYMBOL(fsl_upm_find); * thus UPM pattern actually executed. Note that mar usage depends on the * pre-programmed AMX bits in the UPM RAM. */ + int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar) { int ret = 0; unsigned long flags; + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) + return -ENODEV; + spin_lock_irqsave(&fsl_lbc_lock, flags); - out_be32(&fsl_lbc_regs->mar, mar); + out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar); switch (upm->width) { case 8: @@ -172,3 +159,188 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar) return ret; } EXPORT_SYMBOL(fsl_upm_run_pattern); + +static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl) +{ + struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + + /* clear event registers */ + setbits32(&lbc->ltesr, LTESR_CLEAR); + out_be32(&lbc->lteatr, 0); + out_be32(&lbc->ltear, 0); + out_be32(&lbc->lteccr, LTECCR_CLEAR); + out_be32(&lbc->ltedr, LTEDR_ENABLE); + + /* Enable interrupts for any detected events */ + out_be32(&lbc->lteir, LTEIR_ENABLE); + + return 0; +} + +static int __devexit fsl_lbc_ctrl_remove(struct platform_device *ofdev) +{ + struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev); + + if (ctrl->irq) + free_irq(ctrl->irq, ctrl); + + if (ctrl->regs) + iounmap(ctrl->regs); + + dev_set_drvdata(&ofdev->dev, NULL); + + kfree(ctrl); + + return 0; +} + +/* + * NOTE: This interrupt is used to report localbus events of various kinds, + * such as transaction errors on the chipselects. + */ + +static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data) +{ + struct fsl_lbc_ctrl *ctrl = data; + struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + u32 status; + + status = in_be32(&lbc->ltesr); + + if (status) { + out_be32(&lbc->ltesr, LTESR_CLEAR); + out_be32(&lbc->lteatr, 0); + out_be32(&lbc->ltear, 0); + ctrl->irq_status = status; + + if (status & LTESR_BM) + dev_err(ctrl->dev, "Local bus monitor time-out: " + "LTESR 0x%08X\n", status); + if (status & LTESR_WP) + dev_err(ctrl->dev, "Write protect error: " + "LTESR 0x%08X\n", status); + if (status & LTESR_ATMW) + dev_err(ctrl->dev, "Atomic write error: " + "LTESR 0x%08X\n", status); + if (status & LTESR_ATMR) + dev_err(ctrl->dev, "Atomic read error: " + "LTESR 0x%08X\n", status); + if (status & LTESR_CS) + dev_err(ctrl->dev, "Chip select error: " + "LTESR 0x%08X\n", status); + if (status & LTESR_UPM) + ; + if (status & LTESR_FCT) { + dev_err(ctrl->dev, "FCM command time-out: " + "LTESR 0x%08X\n", status); + smp_wmb(); + wake_up(&ctrl->irq_wait); + } + if (status & LTESR_PAR) { + dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: " + "LTESR 0x%08X\n", status); + smp_wmb(); + wake_up(&ctrl->irq_wait); + } + if (status & LTESR_CC) { + smp_wmb(); + wake_up(&ctrl->irq_wait); + } + if (status & ~LTESR_MASK) + dev_err(ctrl->dev, "Unknown error: " + "LTESR 0x%08X\n", status); + + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +/* + * fsl_lbc_ctrl_probe + * + * called by device layer when it finds a device matching + * one our driver can handled. This code allocates all of + * the resources needed for the controller only. The + * resources for the NAND banks themselves are allocated + * in the chip probe function. +*/ + +static int __devinit fsl_lbc_ctrl_probe(struct platform_device *ofdev, + const struct of_device_id *match) +{ + int ret; + + if (!ofdev->dev.of_node) { + dev_err(&ofdev->dev, "Device OF-Node is NULL"); + return -EFAULT; + } + fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL); + if (!fsl_lbc_ctrl_dev) + return -ENOMEM; + + dev_set_drvdata(&ofdev->dev, fsl_lbc_ctrl_dev); + + spin_lock_init(&fsl_lbc_ctrl_dev->lock); + init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait); + + fsl_lbc_ctrl_dev->regs = of_iomap(ofdev->dev.of_node, 0); + if (!fsl_lbc_ctrl_dev->regs) { + dev_err(&ofdev->dev, "failed to get memory region\n"); + ret = -ENODEV; + goto err; + } + + fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); + if (fsl_lbc_ctrl_dev->irq == NO_IRQ) { + dev_err(&ofdev->dev, "failed to get irq resource\n"); + ret = -ENODEV; + goto err; + } + + fsl_lbc_ctrl_dev->dev = &ofdev->dev; + + ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev); + if (ret < 0) + goto err; + + ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0, + "fsl-lbc", fsl_lbc_ctrl_dev); + if (ret != 0) { + dev_err(&ofdev->dev, "failed to install irq (%d)\n", + fsl_lbc_ctrl_dev->irq); + ret = fsl_lbc_ctrl_dev->irq; + goto err; + } + + return 0; + +err: + iounmap(fsl_lbc_ctrl_dev->regs); + kfree(fsl_lbc_ctrl_dev); + return ret; +} + +static const struct of_device_id fsl_lbc_match[] = { + { .compatible = "fsl,elbc", }, + { .compatible = "fsl,pq3-localbus", }, + { .compatible = "fsl,pq2-localbus", }, + { .compatible = "fsl,pq2pro-localbus", }, + {}, +}; + +static struct of_platform_driver fsl_lbc_ctrl_driver = { + .driver = { + .name = "fsl-lbc", + .of_match_table = fsl_lbc_match, + }, + .probe = fsl_lbc_ctrl_probe, +}; + +static int __init fsl_lbc_init(void) +{ + return of_register_platform_driver(&fsl_lbc_ctrl_driver); +} + +module_init(fsl_lbc_init); +