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[2/2] mtd: fsl_ifc_nand: Workaround bogus WP on 16-bit NAND

Message ID 1267734566.831894.1396889898472.JavaMail.zimbra@xes-inc.com
State Accepted
Commit 2170480487e3dee8a74204ce346b1b1096a13fd0
Headers show

Commit Message

Aaron Sierra April 7, 2014, 4:58 p.m. UTC 
From: Joe Schultz <jschultz@xes-inc.com>

A workaround was already in place that set the WP bit in the
IFC_CSPR0 register after a STATUS command, however it used an 8-bit
write method. As a result, the WP bit was never set on 16-bit devices,
and these devices would eventually be incorrectly marked as
write-protected.

This patch checks the chip options for a 16-bit device and uses the
appropriate write method to set the WP bit after a STATUS command.

Signed-off-by: Joe Schultz <jschultz@xes-inc.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 79941c4..cb329794 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -592,7 +592,10 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		 * The chip always seems to report that it is
 		 * write-protected, even when it is not.
 		 */
-		setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
+		if (chip->options & NAND_BUSWIDTH_16)
+			setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP);
+		else
+			setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
 		return;
 
 	case NAND_CMD_RESET: