| Message ID | cover.1616130675.git.Takahiro.Kuwano@infineon.com |
|---|---|
| Headers | show |
| Series | mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t | expand |
Hi, On 3/19/21 8:51 AM, tkuw584924@gmail.com wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > > The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. > > The summary datasheets can be found in the following links. > https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) > https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) > > The full version can be found in the following links (registration > required). > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 Takahiro, looks like I can't access the dual/quad die full datasheet, not enough rights, even after creating an account. How are multi die ops handled when crossing a die boundary? > > Tested on Xilinx Zynq-7000 FPGA board. Have you tried to erase/read/write multiple dies with a single request? Cheers, ta > > Changes in v4: > - Reword 'legacy' to 'default' > - Rename spi_nor_read() to spi_nor_default_ready() > - Fix dummy cycle calculation in spansion_read_any_reg() > - Modify comment for spansion_write_any_reg() > - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups() > - Remove USE_CLSR flags from S25HL02GT and S25HS02GT > > Changes in v3: > - Split into multiple patches > - Remove S25HL256T and S25HS256T > - Add S25HL02GT and S25HS02GT > - Add support for multi-die package parts support > - Cleanup Read/Write Any Register implementation > - Remove erase_map fix for top/split sector layout > - Set ECC data unit size (16B) to writesize > > Changes in v2: > - Remove SPI_NOR_SKIP_SFDP flag and clean up related fixups > - Check CFR3V[4] to determine page_size instead of force 512B > - Depend on the patchset below to support non-uniform sector layout > https://lore.kernel.org/linux-mtd/cover.1601612872.git.Takahiro.Kuwano@infineon.com/ > > Takahiro Kuwano (6): > mtd: spi-nor: core: Add the ->ready() hook > mtd: spi-nor: core: Expose spi_nor_clear_sr() to manufacturer drivers > mtd: spi-nor: spansion: Add support for Read/Write Any Register > mtd: spi-nor: spansion: Add support for volatile QE bit > mtd: spi-nor: spansion: Add status check for multi-die parts > mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups > > drivers/mtd/spi-nor/core.c | 10 +- > drivers/mtd/spi-nor/core.h | 3 + > drivers/mtd/spi-nor/spansion.c | 325 +++++++++++++++++++++++++++++++++ > 3 files changed, 334 insertions(+), 4 deletions(-) > > -- > 2.25.1 >
Hi Tudor, On 4/1/2021 3:09 PM, Tudor.Ambarus@microchip.com wrote: > Hi, > > On 3/19/21 8:51 AM, tkuw584924@gmail.com wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> >> >> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >> >> The summary datasheets can be found in the following links. >> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) >> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) >> >> The full version can be found in the following links (registration >> required). >> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 >> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 > > Takahiro, looks like I can't access the dual/quad die full datasheet, not enough rights, > even after creating an account. > My colleague helped on this. I hope you could access the datasheet. > How are multi die ops handled when crossing a die boundary? > The existing erase/write ops are done by sector/page size alignment and never cross a die boundary. The read ops does not care about die boundary but still works because the Semper dual/quad die parts continue to output data from next die when crossing a die boundary. >> >> Tested on Xilinx Zynq-7000 FPGA board. > > Have you tried to erase/read/write multiple dies with a single request? > Yes, I did 'mtd_debug erase/write/read' with address ranges that involve two dies. You can find errata info in the datasheet about cross-die read. My test does not cover the trigger condition of the failure actually. I will submit another patch that work around the issue as needed. Best Regards, Takahiro
On 4/2/21 10:13 AM, Takahiro Kuwano wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Tudor, Hi! > > On 4/1/2021 3:09 PM, Tudor.Ambarus@microchip.com wrote: >> Hi, >> >> On 3/19/21 8:51 AM, tkuw584924@gmail.com wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> >>> >>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >>> >>> The summary datasheets can be found in the following links. >>> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) >>> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) >>> >>> The full version can be found in the following links (registration >>> required). >>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 >>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 >> >> Takahiro, looks like I can't access the dual/quad die full datasheet, not enough rights, >> even after creating an account. >> > My colleague helped on this. I hope you could access the datasheet. Takahiro, I can now access the datasheet, thanks! I see that Erase Chip requires an address. Is the erase chip with address common to other manufacturers? We'll have to update the core so that these flashe benefit of the erase chip opcode. Otherwise we'll have to set SNOR_F_NO_OP_CHIP_ERASE at flash declaration, which I don't really favor. > >> How are multi die ops handled when crossing a die boundary? >> > The existing erase/write ops are done by sector/page size alignment and > never cross a die boundary. The read ops does not care about die boundary What do you mean? What will happen if I request to erase 512K starting from offset (die0 - 256K)? > but still works because the Semper dual/quad die parts continue to output > data from next die when crossing a die boundary. cool > >>> >>> Tested on Xilinx Zynq-7000 FPGA board. >> >> Have you tried to erase/read/write multiple dies with a single request? >> > Yes, I did 'mtd_debug erase/write/read' with address ranges that involve > two dies. You can find errata info in the datasheet about cross-die read. > My test does not cover the trigger condition of the failure actually. > I will submit another patch that work around the issue as needed. > How will you differentiate between silicon revisions? Cheers, ta
On 4/8/2021 2:35 PM, Tudor.Ambarus@microchip.com wrote: > On 4/2/21 10:13 AM, Takahiro Kuwano wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> Hi Tudor, > > Hi! > >> >> On 4/1/2021 3:09 PM, Tudor.Ambarus@microchip.com wrote: >>> Hi, >>> >>> On 3/19/21 8:51 AM, tkuw584924@gmail.com wrote: >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>> >>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> >>>> >>>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >>>> >>>> The summary datasheets can be found in the following links. >>>> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) >>>> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) >>>> >>>> The full version can be found in the following links (registration >>>> required). >>>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 >>>> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 >>> >>> Takahiro, looks like I can't access the dual/quad die full datasheet, not enough rights, >>> even after creating an account. >>> >> My colleague helped on this. I hope you could access the datasheet. > > Takahiro, I can now access the datasheet, thanks! I see that Erase Chip > requires an address. Is the erase chip with address common to other > manufacturers? We'll have to update the core so that these flashe > benefit of the erase chip opcode. Otherwise we'll have to set > SNOR_F_NO_OP_CHIP_ERASE at flash declaration, which I don't really favor. > I overlooked the erase chip for multi-die package parts. Thank you for pointing this out. I checked Micron MT25QL02GCBB datasheet and found the part supports DIE ERASE (C4h) instead of standard CHIP ERASE. https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf?rev=43f7f66fc8da4d7d901b35fa51284c8f To support die erase, the core needs to know die size. That will initiate a discussion about overall support for multi-die package devices. I think it's better to create another series of patches for that. In this series, I would set SNOR_F_NO_OP_CHIP_ERASE as a temporary solution. >> >>> How are multi die ops handled when crossing a die boundary? >>> >> The existing erase/write ops are done by sector/page size alignment and >> never cross a die boundary. The read ops does not care about die boundary > > What do you mean? What will happen if I request to erase 512K starting from > offset (die0 - 256K)? > I meant the erase and write requests are split into multiple ops based on sector or page size. So, if you request to erase 512K starting from there, two erase ops will be performed. One is for the last sector in die0 and another is for the first sector in die1. >> but still works because the Semper dual/quad die parts continue to output >> data from next die when crossing a die boundary. > > cool > >> >>>> >>>> Tested on Xilinx Zynq-7000 FPGA board. >>> >>> Have you tried to erase/read/write multiple dies with a single request? >>> >> Yes, I did 'mtd_debug erase/write/read' with address ranges that involve >> two dies. You can find errata info in the datasheet about cross-die read. >> My test does not cover the trigger condition of the failure actually. >> I will submit another patch that work around the issue as needed. >> > > How will you differentiate between silicon revisions? > No way to differentiate. So, if I apply a workaround like splitting a read request into two read ops, that is performed for newer silicon even though it is not needed. I would like to implement the workaround once I find it is a real issue on many systems. Best Regards, Takahiro
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. The summary datasheets can be found in the following links. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 Tested on Xilinx Zynq-7000 FPGA board. Changes in v4: - Reword 'legacy' to 'default' - Rename spi_nor_read() to spi_nor_default_ready() - Fix dummy cycle calculation in spansion_read_any_reg() - Modify comment for spansion_write_any_reg() - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups() - Remove USE_CLSR flags from S25HL02GT and S25HS02GT Changes in v3: - Split into multiple patches - Remove S25HL256T and S25HS256T - Add S25HL02GT and S25HS02GT - Add support for multi-die package parts support - Cleanup Read/Write Any Register implementation - Remove erase_map fix for top/split sector layout - Set ECC data unit size (16B) to writesize Changes in v2: - Remove SPI_NOR_SKIP_SFDP flag and clean up related fixups - Check CFR3V[4] to determine page_size instead of force 512B - Depend on the patchset below to support non-uniform sector layout https://lore.kernel.org/linux-mtd/cover.1601612872.git.Takahiro.Kuwano@infineon.com/ Takahiro Kuwano (6): mtd: spi-nor: core: Add the ->ready() hook mtd: spi-nor: core: Expose spi_nor_clear_sr() to manufacturer drivers mtd: spi-nor: spansion: Add support for Read/Write Any Register mtd: spi-nor: spansion: Add support for volatile QE bit mtd: spi-nor: spansion: Add status check for multi-die parts mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups drivers/mtd/spi-nor/core.c | 10 +- drivers/mtd/spi-nor/core.h | 3 + drivers/mtd/spi-nor/spansion.c | 325 +++++++++++++++++++++++++++++++++ 3 files changed, 334 insertions(+), 4 deletions(-)