Message ID | 20210526181636.1130-1-macroalpha82@gmail.com |
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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id j20sm4148311oot.29.2021.05.26.11.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 11:16:47 -0700 (PDT) From: Chris Morgan <macroalpha82@gmail.com> To: linux-mtd@lists.infradead.org Cc: linux-rockchip@lists.infradead.org, andy.yan@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, tudor.ambarus@microchip.com, michael@walle.cc, p.yadav@ti.com, heiko@sntech.de, robh+dt@kernel.org, vigneshr@ti.com, richard@nod.at, miquel.raynal@bootlin.com, Chris Morgan <macromorgan@hotmail.com> Subject: [PATCH 0/3] Add Rockchip SFC(serial flash controller) support Date: Wed, 26 May 2021 13:16:33 -0500 Message-Id: <20210526181636.1130-1-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210526_111650_320464_55B09431 X-CRM114-Status: GOOD ( 15.87 ) X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan I'm trying to revive an abandoned patch series for the Rockchip serial flash controller (SFC) found on the Rockchip PX30 SOC, as well as other SOCs by Rockchip. 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Add Rockchip SFC(serial flash controller) support
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From: Chris Morgan <macromorgan@hotmail.com> I'm trying to revive an abandoned patch series for the Rockchip serial flash controller (SFC) found on the Rockchip PX30 SOC, as well as other SOCs by Rockchip. I'm picking this up from version 8 of the patch series located from here: http://patchwork.ozlabs.org/project/linux-mtd/cover/1518091958-3672-1-git-send-email-andy.yan@rock-chips.com/ Changes made in this new series versus the v8 of the old series: - Added function to read spi-rx-bus-width from device tree, in the event that the SPI chip supports 4x mode but only has 2 pins wired (such as the Odroid Go Advance). - Changed device tree documentation from txt to yaml format. - Made "reset" message a dev_dbg from a dev_info. - Changed read and write fifo functions to remove redundant checks. - Changed the write and read from relaxed to non-relaxed when starting the DMA transfer or reading the DMA IRQ. - Changed from dma_coerce_mask_and_coherent to just dma_set_mask_and_coherent. - Changed name of get_if_type to rockchip_sfc_get_if_type. Chris Morgan (3): mtd: spi-nor: add rockchip serial flash controller driver mtd: spi-nor: Bindings for Rockchip serial flash controller arm64: dts: rockchip: Add SFC to PX30 .../mtd/rockchip,serialflash-controller.yaml | 100 ++ arch/arm64/boot/dts/rockchip/px30.dtsi | 38 + drivers/mtd/spi-nor/controllers/Kconfig | 7 + drivers/mtd/spi-nor/controllers/Makefile | 1 + .../mtd/spi-nor/controllers/rockchip-sfc.c | 944 ++++++++++++++++++ 5 files changed, 1090 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml create mode 100644 drivers/mtd/spi-nor/controllers/rockchip-sfc.c