[GIT,PULL,6/7] Renesas RISC-V DT updates for v6.2

Message ID	cover.1668788930.git.geert+renesas@glider.be
State	New
Headers	show Return-Path: <linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org> From: Geert Uytterhoeven <geert+renesas@glider.be> To: arm-soc <arm@kernel.org>, soc <soc@kernel.org> Cc: Magnus Damm <magnus.damm@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven <geert+renesas@glider.be> Subject: [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2 Date: Fri, 18 Nov 2022 17:45:03 +0100 Message-Id: <cover.1668788930.git.geert+renesas@glider.be> In-Reply-To: <cover.1668788918.git.geert+renesas@glider.be> References: <cover.1668788918.git.geert+renesas@glider.be> MIME-Version: 1.0 preview: The following changes since commit b9a0be2054964026aa58966ce9724b672f210835: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts (2022-10-28 14:23:00 +0200) are available in the Git repository at: Content analysis details: (-0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [2a02:1800:120:4:0:0:f00:13 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org
Series	Renesas SoC updates for v6.2 (take two) \| expand [GIT,PULL,0/7] Renesas SoC updates for v6.2 (take two) [GIT,PULL,1/7] Renesas ARM defconfig updates for v6.2 [GIT,PULL,2/7] Renesas ARM DT updates for v6.2 (take two) [GIT,PULL,3/7] Renesas driver updates for v6.2 (take two) [GIT,PULL,4/7] Renesas DT binding updates for v6.2 (take two) [GIT,PULL,5/7] Renesas RISC-V defconfig updates for v6.2 [GIT,PULL,6/7] Renesas RISC-V DT updates for v6.2 [GIT,PULL,7/7] Renesas RISC-V SoC updates for v6.2

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cover.1668788930.git.geert+renesas@glider.be

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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: arm-soc <arm@kernel.org>,
	soc <soc@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2
Date: Fri, 18 Nov 2022 17:45:03 +0100
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Series

Renesas SoC updates for v6.2 (take two) | expand

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Geert Uytterhoeven Nov. 18, 2022, 4:45 p.m. UTC

The following changes since commit b9a0be2054964026aa58966ce9724b672f210835:

  arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts (2022-10-28 14:23:00 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-riscv-dt-for-v6.2-tag1

for you to fetch changes up to 40005cb6093e92d24a1bdbc444311c25e4b28878:

  riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C (2022-11-17 20:27:02 +0100)

----------------------------------------------------------------
Renesas RISC-V DT updates for v6.2

  - Add initial support for the Renesas RZ/Five SoC and the Renesas
    RZ/Five SMARC EVK development board.

----------------------------------------------------------------
Lad Prabhakar (5):
      riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
      riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
      MAINTAINERS: Add entry for Renesas RISC-V
      riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
      riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C

 MAINTAINERS                                        |  3 +-
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/renesas/Makefile               |  2 +
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi        | 59 ++++++++++++++++++++
 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++
 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi  | 47 ++++++++++++++++
 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi      | 64 ++++++++++++++++++++++
 7 files changed, 202 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/boot/dts/renesas/Makefile
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi

[GIT,PULL,6/7] Renesas RISC-V DT updates for v6.2

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