From patchwork Tue Oct 17 12:47:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 826959 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HlAm2OzP"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yGZlk6Nhdz9rxl for ; Tue, 17 Oct 2017 23:49:54 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0J9MpDoyBkUZ6VPz9iLMMbiIeOBaLz0WE1XwG4j634s=; b=HlAm2OzPG9pdki kB05YaPyGlcLhso+LLuRmBwe6OMWAxENWljXfJ+wsAL0FXhLzrCis85AviM16hq26boUp7XcH8Ete EwL88WQe5fxiQReZkFOIl1n8LhH93fEyZTXfbVLPhmXRP6opyOxgYzx8WM3hGHYnyO+J4FFlmuaOK JQ9uJ623vZ8ZRfnDY4dQdp8sOjaGWnwU0b2LF/70yREbzNwO3hNQJ3KLTRsjpK5aLh4BHclOPv4cv 9bIf4lVa/g/jvfsaYpbM7l9Cs1H8zUcvIa8Y4q7YxrgpZbZxbpCN6EjrcG4xSqYW5hrFD+Wjtj0tK fFRpLRQKBSPc3NBjlBHA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1e4RJa-00065e-5T; Tue, 17 Oct 2017 12:49:46 +0000 Received: from mx2.suse.de ([195.135.220.15]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1e4RHx-0004JY-NQ for linux-arm-kernel@lists.infradead.org; Tue, 17 Oct 2017 12:48:15 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id B71F2ACFF; Tue, 17 Oct 2017 12:47:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/5] irqchip: rtd119x: Add RTD1195 definitions Date: Tue, 17 Oct 2017 14:47:07 +0200 Message-Id: <20171017124708.6242-6-afaerber@suse.de> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171017124708.6242-1-afaerber@suse.de> References: <20171017124708.6242-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171017_054806_550382_D4D8D268 X-CRM114-Status: GOOD ( 10.66 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?b?6JKL5Li955C0?= , Bizon , linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Roc He Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Add compatible strings and bit definitions for Realtek RTD1195 SoC. Signed-off-by: Andreas Färber --- v3: New drivers/irqchip/irq-rtd119x-mux.c | 99 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-rtd119x-mux.c b/drivers/irqchip/irq-rtd119x-mux.c index ad6e2093fcd3..84c592ad7421 100644 --- a/drivers/irqchip/irq-rtd119x-mux.c +++ b/drivers/irqchip/irq-rtd119x-mux.c @@ -1,5 +1,5 @@ /* - * Realtek RTD129x IRQ mux + * Realtek RTD119x/RTD129x IRQ mux * * Copyright (c) 2017 Andreas Färber * @@ -144,6 +144,81 @@ static struct irq_domain_ops rtd119x_mux_irq_domain_ops = { .map = rtd119x_mux_irq_domain_map, }; +enum rtd119x_iso_isr_bits { + RTD119X_ISO_ISR_TC3_SHIFT = 1, + RTD119X_ISO_ISR_UR0_SHIFT = 2, + RTD119X_ISO_ISR_IRDA_SHIFT = 5, + RTD119X_ISO_ISR_WDOG_NMI_SHIFT = 7, + RTD119X_ISO_ISR_I2C0_SHIFT = 8, + RTD119X_ISO_ISR_TC4_SHIFT = 9, + RTD119X_ISO_ISR_I2C6_SHIFT = 10, + RTD119X_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD119X_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD119X_ISO_ISR_VFD_WDONE_SHIFT = 14, + RTD119X_ISO_ISR_VFD_ARDKPADA_SHIFT = 15, + RTD119X_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16, + RTD119X_ISO_ISR_VFD_ARDSWA_SHIFT = 17, + RTD119X_ISO_ISR_VFD_ARDSWDA_SHIFT = 18, + RTD119X_ISO_ISR_GPIOA_SHIFT = 19, + RTD119X_ISO_ISR_GPIODA_SHIFT = 20, + RTD119X_ISO_ISR_CEC_SHIFT = 22, +}; + +static const u32 rtd119x_iso_isr_to_scpu_int_en_mask[32] = { + [RTD119X_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD119X_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD119X_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD119X_ISO_ISR_I2C6_SHIFT] = BIT(10), + [RTD119X_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD119X_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD119X_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14), + [RTD119X_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15), + [RTD119X_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16), + [RTD119X_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17), + [RTD119X_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18), + [RTD119X_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD119X_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD119X_ISO_ISR_CEC_SHIFT] = BIT(22), +}; + +enum rtd119x_misc_isr_bits { + RTD119X_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD119X_MIS_ISR_UR1_SHIFT, + RTD119X_MIS_ISR_I2C1_SHIFT, + RTD119X_MIS_ISR_UR1_TO_SHIFT, + RTD119X_MIS_ISR_TC0_SHIFT, + RTD119X_MIS_ISR_TC1_SHIFT, + RTD119X_MIS_ISR_RTC_HSEC_SHIFT = 9, + RTD119X_MIS_ISR_RTC_MIN_SHIFT, + RTD119X_MIS_ISR_RTC_HOUR_SHIFT, + RTD119X_MIS_ISR_RTC_DATE_SHIFT, + RTD119X_MIS_ISR_I2C5_SHIFT = 14, + RTD119X_MIS_ISR_I2C4_SHIFT, + RTD119X_MIS_ISR_GPIOA_SHIFT = 19, + RTD119X_MIS_ISR_GPIODA_SHIFT, + RTD119X_MIS_ISR_LSADC_SHIFT, + RTD119X_MIS_ISR_I2C3_SHIFT = 23, + RTD119X_MIS_ISR_I2C2_SHIFT = 26, + RTD119X_MIS_ISR_GSPI_SHIFT, +}; + +static const u32 rtd119x_misc_isr_to_scpu_int_en_mask[32] = { + [RTD119X_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD119X_MIS_ISR_I2C1_SHIFT] = BIT(4), + [RTD119X_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD119X_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD119X_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD119X_MIS_ISR_RTC_DATE_SHIFT] = BIT(12), + [RTD119X_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD119X_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD119X_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD119X_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD119X_MIS_ISR_LSADC_SHIFT] = BIT(21), + [RTD119X_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD119X_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD119X_MIS_ISR_I2C3_SHIFT] = BIT(28), +}; + enum rtd129x_iso_isr_bits { RTD1295_ISO_ISR_UR0_SHIFT = 2, RTD1295_ISO_ISR_IRDA_SHIFT = 5, @@ -214,6 +289,13 @@ static const u32 rtd129x_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_ISR_FAN_SHIFT] = BIT(29), }; +static const struct rtd119x_irq_mux_info rtd119x_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_scpu_int_en_mask = rtd119x_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd119x_irq_mux_info rtd129x_iso_irq_mux_info = { .isr_offset = 0x0, .umsk_isr_offset = 0x4, @@ -221,6 +303,13 @@ static const struct rtd119x_irq_mux_info rtd129x_iso_irq_mux_info = { .isr_to_scpu_int_en_mask = rtd129x_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd119x_irq_mux_info rtd119x_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_scpu_int_en_mask = rtd119x_misc_isr_to_scpu_int_en_mask, +}; + static const struct rtd119x_irq_mux_info rtd129x_misc_irq_mux_info = { .umsk_isr_offset = 0x8, .isr_offset = 0xc, @@ -230,9 +319,15 @@ static const struct rtd119x_irq_mux_info rtd129x_misc_irq_mux_info = { static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { { + .compatible = "realtek,rtd1195-iso-irq-mux", + .data = &rtd119x_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd129x_iso_irq_mux_info, }, { + .compatible = "realtek,rtd1195-misc-irq-mux", + .data = &rtd119x_misc_irq_mux_info, + }, { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd129x_misc_irq_mux_info, }, { @@ -287,5 +382,7 @@ static int __init rtd119x_irq_mux_init(struct device_node *node, return 0; } +IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd119x_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd119x_irq_mux_init); +IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd119x_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd119x_irq_mux_init);