From patchwork Sat Jul 1 21:29:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 783130 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x0RQP2m1qz9sQl for ; Sun, 2 Jul 2017 07:30:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FpUxnuoW"; dkim-atps=neutral DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2QS9TzGCPYO/+tqdN+lJ4elREAPtDKDpPrtq3ZKhmKA=; b=FpUxnuoWfZ8P6T iwd7z169NY/Xd5Il76cUHdS+g04CNaKORnikEC4yjcMSFTs1H/eG7u5axwi3R8vrY/PQeBH8O41pW GYObdLjkHyGB1+Zvy88Ve9YoD/aCFX81LTbeL3w9rE7893eLxJE+tFupKnV/yHsvmSMnxtERqzvWZ +agQEEz+FlaXT22M3DuWd4eo16SlchN/ayL531J3yx6LiuuuaRTYhyeC+eeU9m46oQRvP8MxFVw2F /cfmBGH++LKdXfs3A3SOhUdESanWi05QsNq1V2eO6B5mkWqAg6BVI+9PJ6widH0uSI97QpFRYGrhS /oLFiUWzipKnKUSIPwHw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dRPyM-0007ek-KL; Sat, 01 Jul 2017 21:30:34 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dRPyH-0007Is-Qe for linux-arm-kernel@lists.infradead.org; Sat, 01 Jul 2017 21:30:32 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id B1092AAB9; Sat, 1 Jul 2017 21:30:06 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: owl: smp: Drop bogus holding pen Date: Sat, 1 Jul 2017 23:29:30 +0200 Message-Id: <20170701212930.606-1-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170701_143030_479894_60570297 X-CRM114-Status: GOOD ( 13.40 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: support@lemaker.org, =?UTF-8?q?=E5=BC=A0=E5=A4=A9=E7=9B=8A?= , Arnd Bergmann , =?UTF-8?q?=E6=A2=85=E5=88=A9?= , linux-kernel@vger.kernel.org, Thomas Liau , Russell King , support@cubietech.com, lee@cubietech.com, mp-cs@actions-semi.com, =?UTF-8?q?=E5=88=98=E7=82=9C?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?=E5=BC=A0=E4=B8=9C=E9=A3=8E?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The S500 SoC can start secondary CPUs without busy-looping for pen_release, so simplify the SMP code compared to the LeMaker kernel tree. Fixes: 172067e0bc87 ("ARM: owl: Implement CPU enable-method for S500") Suggested-by: Arnd Bergmann Cc: David Liu Signed-off-by: Andreas Färber --- arch/arm/mach-actions/headsmp.S | 20 ++------------------ arch/arm/mach-actions/platsmp.c | 29 +---------------------------- 2 files changed, 3 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S index dc4832fc101a..65f53bdb69e7 100644 --- a/arch/arm/mach-actions/headsmp.S +++ b/arch/arm/mach-actions/headsmp.S @@ -2,6 +2,8 @@ * Copyright 2012 Actions Semi Inc. * Author: Actions Semi, Inc. * + * Copyright (c) 2017 Andreas Färber + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -46,23 +48,5 @@ ENTRY(owl_v7_invalidate_l1) ENDPROC(owl_v7_invalidate_l1) ENTRY(owl_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #0xf - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: - ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ bl owl_v7_invalidate_l1 b secondary_startup - -1: .long . - .long pen_release diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index b4806ce0e9bb..12a9e331b432 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -41,26 +41,6 @@ static int ncores; static DEFINE_SPINLOCK(boot_lock); -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void s500_smp_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - void owl_secondary_startup(void); static int s500_wakeup_secondary(unsigned int cpu) @@ -115,12 +95,6 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) spin_lock(&boot_lock); - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - */ - write_pen_release(cpu_logical_map(cpu)); smp_send_reschedule(cpu); timeout = jiffies + (1 * HZ); @@ -134,7 +108,7 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) spin_unlock(&boot_lock); - return pen_release != -1 ? -ENOSYS : 0; + return 0; } static void __init s500_smp_prepare_cpus(unsigned int max_cpus) @@ -192,7 +166,6 @@ static void __init s500_smp_prepare_cpus(unsigned int max_cpus) static const struct smp_operations s500_smp_ops __initconst = { .smp_prepare_cpus = s500_smp_prepare_cpus, - .smp_secondary_init = s500_smp_secondary_init, .smp_boot_secondary = s500_smp_boot_secondary, }; CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops);