From patchwork Sat Jan 7 05:58:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 134752 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F1D7DB6F70 for ; Sat, 7 Jan 2012 16:50:58 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RjP8S-0007Hu-RJ; Sat, 07 Jan 2012 05:48:09 +0000 Received: from mail-iy0-f177.google.com ([209.85.210.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RjP8P-0007Hg-G2 for linux-arm-kernel@lists.infradead.org; Sat, 07 Jan 2012 05:48:06 +0000 Received: by iadk27 with SMTP id k27so4378511iad.36 for ; Fri, 06 Jan 2012 21:48:04 -0800 (PST) Received: by 10.42.150.130 with SMTP id a2mr8065440icw.43.1325915284662; Fri, 06 Jan 2012 21:48:04 -0800 (PST) Received: from S2101-09.ap.freescale.net ([114.216.146.193]) by mx.google.com with ESMTPS id x18sm222058669ibi.2.2012.01.06.21.47.51 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 Jan 2012 21:48:03 -0800 (PST) Date: Sat, 7 Jan 2012 13:58:20 +0800 From: Shawn Guo To: Thierry Reding Subject: Re: [PATCH] irqdomain: Initialize number of IRQs for simple domains Message-ID: <20120107055817.GG4790@S2101-09.ap.freescale.net> References: <1325860112-22051-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1325860112-22051-1-git-send-email-thierry.reding@avionic-design.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.1 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.5 SINGLE_HEADER_1K A single header contains 1K-2K characters Cc: Tony Lindgren , Catalin Marinas , Nicolas Ferre , Grant Likely , Daniel Walker , Jamie Iles , Russell King , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , David Brown , Jean-Christophe Plagniol-Villard , "open list:ARM/QUALCOMM MSM..." , devicetree-discuss@lists.ozlabs.org, Rob Herring , Barry Song , Thomas Gleixner , "open list:OMAP SUPPORT" , Andrew Victor , "open list:ARM/ATMEL AT91RM9..." , open list , Bryan Huntsman , Richard Zhao , Sascha Hauer , David Woodhouse X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi Thierry, On Fri, Jan 06, 2012 at 03:28:25PM +0100, Thierry Reding wrote: > The irq_domain_add() function needs the number of interrupts in the > domain to properly initialize them. In addition the allocated domain > is now returned by the irq_domain_{add,generate}_simple() helpers. > > Signed-off-by: Thierry Reding > --- ... > arch/arm/mach-imx/imx51-dt.c | 13 +++++++++++-- > arch/arm/mach-imx/imx53-dt.c | 13 +++++++++++-- > arch/arm/mach-imx/mach-imx6q.c | 4 +++- ... > arch/arm/plat-mxc/include/mach/irqs.h | 1 + > arch/arm/plat-mxc/tzic.c | 2 -- Thanks for patching imx. It looks good to me, except a couple minor comments below. ... > diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c > index e6bad17..72bf94c 100644 > --- a/arch/arm/mach-imx/imx51-dt.c > +++ b/arch/arm/mach-imx/imx51-dt.c > @@ -47,7 +47,12 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { > static int __init imx51_tzic_add_irq_domain(struct device_node *np, > struct device_node *interrupt_parent) > { > - irq_domain_add_simple(np, 0); > + struct irq_domain *domain; > + > + domain = irq_domain_add_simple(np, 0, TZIC_NUM_IRQS); > + if (IS_ERR(domain)) > + return PTR_ERR(domain); > + > return 0; > } > > @@ -55,9 +60,13 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np, > struct device_node *interrupt_parent) > { > static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; > + struct irq_domain *domain; > > gpio_irq_base -= 32; > - irq_domain_add_simple(np, gpio_irq_base); > + > + domain = irq_domain_add_simple(np, gpio_irq_base, 32); > + if (IS_ERR(domain)) > + return PTR_ERR(domain); > > return 0; > } > diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c > index 05ebb3e..ccae620 100644 > --- a/arch/arm/mach-imx/imx53-dt.c > +++ b/arch/arm/mach-imx/imx53-dt.c > @@ -51,7 +51,12 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { > static int __init imx53_tzic_add_irq_domain(struct device_node *np, > struct device_node *interrupt_parent) > { > - irq_domain_add_simple(np, 0); > + struct irq_domain *domain; > + > + domain = irq_domain_add_simple(np, 0, TZIC_NUM_IRQS); > + if (IS_ERR(domain)) > + return PTR_ERR(domain); > + > return 0; > } > > @@ -59,9 +64,13 @@ static int __init imx53_gpio_add_irq_domain(struct device_node *np, > struct device_node *interrupt_parent) > { > static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; > + struct irq_domain *domain; > > gpio_irq_base -= 32; > - irq_domain_add_simple(np, gpio_irq_base); > + > + domain = irq_domain_add_simple(np, gpio_irq_base, 32); > + if (IS_ERR(domain)) > + return PTR_ERR(domain); > > return 0; > } > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c > index c257281..9ed7812 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -95,9 +95,11 @@ static int __init imx6q_gpio_add_irq_domain(struct device_node *np, > struct device_node *interrupt_parent) > { > static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; > + struct irq_domain *domain; > > gpio_irq_base -= 32; > - irq_domain_add_simple(np, gpio_irq_base); > + domain = irq_domain_add_simple(np, gpio_irq_base, 32); > + WARN_ON(IS_ERR(domain)); Why do we handle the error in a different pattern that is used for all above? > > return 0; > } ... > diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h > index fd9efb0..2fda5aa 100644 > --- a/arch/arm/plat-mxc/include/mach/irqs.h > +++ b/arch/arm/plat-mxc/include/mach/irqs.h > @@ -54,6 +54,7 @@ > /* REVISIT: Add IPU irqs on IMX51 */ > > #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) > +#define TZIC_NUM_IRQS 128 > > extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); > I just made a small change on top of yours. Can you please consider to amend it to your patch if it looks sane to you? diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 2fda5aa..70376e0 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -13,19 +13,20 @@ #include +#define GIC_NUM_IRQS 160 +#define TZIC_NUM_IRQS 128 +#define AVIC_NUM_IRQS 64 + /* - * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC - * have 128 IRQs, and those with AVIC have 64. - * * To support single image, the biggest number should be defined on * top of the list. */ #if defined CONFIG_ARM_GIC -#define MXC_INTERNAL_IRQS 160 +#define MXC_INTERNAL_IRQS GIC_NUM_IRQS #elif defined CONFIG_MXC_TZIC -#define MXC_INTERNAL_IRQS 128 +#define MXC_INTERNAL_IRQS TZIC_NUM_IRQS #else -#define MXC_INTERNAL_IRQS 64 +#define MXC_INTERNAL_IRQS AVIC_NUM_IRQS #endif #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS @@ -54,7 +55,6 @@ /* REVISIT: Add IPU irqs on IMX51 */ #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) -#define TZIC_NUM_IRQS 128 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);