From patchwork Thu Aug 21 16:51:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 382001 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1941C1400AB for ; Fri, 22 Aug 2014 02:53:35 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XKVaN-0002dv-QJ; Thu, 21 Aug 2014 16:51:39 +0000 Received: from f420.i.mail.ru ([185.5.136.91]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XKVaK-0002Qv-Sr for linux-arm-kernel@lists.infradead.org; Thu, 21 Aug 2014 16:51:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Content-Transfer-Encoding:Content-Type:Message-ID:Reply-To:Date:Mime-Version:Subject:Cc:To:From; bh=vSQ2a5tYrm2kDg+3Cd7yWeE2xz7VbScTsCw7ylIEXZk=; b=sUJjiUoUhFiBW6qwtn67WzNIL1WGU0ZwCIMQyBNnO2vVWnGo4+u5dEsNwCQ1mKQoLZp2L8LmGbbgUunlyrx5q/Llkf1v6er6EpL8EOJblDR5yjWr+LWNQVo1lc+v3tsYbqFZVYpS2IwO8YEsn6IsGfyU4bA1al7HQehdkdifXmQ=; Received: from [5.18.98.7] (ident=mail) by f420.i.mail.ru with local (envelope-from ) id 1XKVZy-0005tc-7w; Thu, 21 Aug 2014 20:51:14 +0400 Received: from [5.18.98.7] by e.mail.ru with HTTP; Thu, 21 Aug 2014 20:51:14 +0400 From: =?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?= To: =?UTF-8?B?R3J5Z29yaWkgU3RyYXNoa28=?= Subject: =?UTF-8?B?UmU6IFtQQVRDSCB2MiAwLzNdIGdwaW86IHN5c2NvbjogcmV1c2UgZm9yIGtl?= =?UTF-8?B?eXN0b25lIDIgc29jcw==?= Mime-Version: 1.0 X-Mailer: Mail.Ru Mailer 1.0 X-Originating-IP: [5.18.98.7] Date: Thu, 21 Aug 2014 20:51:14 +0400 X-Priority: 3 (Normal) Message-ID: <1408639874.873856101@f420.i.mail.ru> X-Cloud-Ids: X-Mras: Ok X-Spam: undefined In-Reply-To: <1408638203-8246-1-git-send-email-grygorii.strashko@ti.com> References: <53ECE9B1.4060303@ti.com> <1408638203-8246-1-git-send-email-grygorii.strashko@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140821_095137_342357_B81F3EA1 X-CRM114-Status: GOOD ( 22.73 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [185.5.136.91 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shc_work[at]mail.ru) -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.1 FROM_EXCESS_BASE64 From: base64 encoded unnecessarily Cc: =?UTF-8?B?QWxleGFuZHJlIENvdXJib3Q=?= , devicetree@vger.kernel.org, =?UTF-8?B?TGludXMgV2FsbGVpag==?= , linux-gpio@vger.kernel.org, =?UTF-8?B?Um9iIEhlcnJpbmc=?= , santosh.shilimkar@ti.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: =?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Thu, 21 Aug 2014 19:23:20 +0300 от Grygorii Strashko : > Hi All, > > Alexander, > > I've updated gpio-syscon as requested in [3]. > I still don't like it, but any way I did it :( > > Linus, > > I'd very appreciated if you can comment on these series. > Personally, I like v1 [3], because this v2 is not elegant and will > require constant code patching in case of adding new SoCs or new SoC's versions. > > This series intended to integrate Keystone 2 DSP GPIO controller functionality > into gpio-syscon driver (drivers/gpio/gpio-syscon.c) as requested > by Linus Walleij in [1]. > > On Keystone SOCs, ARM host can send interrupts to DSP cores using the > DSP GPIO controller IP. Each DSP GPIO controller provides 28 IRQ signals for > each DSP core. This is one of the component used by the IPC mechanism used > on Keystone SOCs. > > Keystone 2 DSP GPIO controller has specific features: > - each GPIO can be configured only as output pin; > - setting GPIO value to 1 causes IRQ generation on target DSP core; > - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still > pending. > > The gpio-syscon driver was need to be updated to satisfy Keystone 2 SoC > requirements: > - special sequence of operations need to be used to assign output GPIO value. > As result, first patch introduces SoC specific callback .set() to configure > output GPIO value. > > Also, patch 3 was added to illustrate DSP GPIO configuration in DT used by Keystone 2. > > Related sicussions: > [1] https://lkml.org/lkml/2014/7/16/170 > [2] https://lkml.org/lkml/2014/7/23/352 > [3] https://www.mail-archive.com/devicetree@vger.kernel.org/msg37863.html > > Grygorii Strashko (3): > gpio: syscon: add soc specific callback to assign output value > gpio: syscon: reuse for keystone 2 socs > ARM: dts: keystone-k2hk: add dsp gpio controllers nodes > > .../bindings/gpio/gpio-mctrl-keystone.txt | 42 ++++++ > arch/arm/boot/dts/k2hk.dtsi | 48 +++++++ > drivers/gpio/gpio-syscon.c | 140 ++++++++++++++++++++ > 3 files changed, 230 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mctrl-keystone.txt 1. mctrl -> dsp in filenames 2. mctrl -> dsp in documentation. 3. Here is a more elegant solution for first part. --- gpio-syscon.c.old 2014-08-19 09:46:09.000000000 +0400 +++ gpio-syscon.c 2014-08-21 20:45:49.357529323 +0400 @@ -111,7 +111,7 @@ BIT(offs % SYSCON_REG_BITS)); } - syscon_gpio_set(chip, offset, val); + priv->data->set(chip, offset, val); return 0; } @@ -159,7 +159,7 @@ if (priv->data->flags & GPIO_SYSCON_FEAT_IN) priv->chip.direction_input = syscon_gpio_dir_in; if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { - priv->chip.set = syscon_gpio_set; + priv->chip.set = priv->data->set ? : syscon_gpio_set; priv->chip.direction_output = syscon_gpio_dir_out; }