| Message ID | 1385399751-19109-3-git-send-email-mkl@pengutronix.de |
|---|---|
| State | New |
| Headers | show |
> This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the > lp_apm clock, which has a rate of 24 MHz. > > In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA > recommented bit rates. Without this patch the CAN peripheral clock on i.MX53 > has a rate of 66.666 MHz which produces quite large bit rate errors. > > Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> > --- > arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c > index e349fd5..28f7f3f 100644 > --- a/arch/arm/mach-imx/clk-imx51-imx53.c > +++ b/arch/arm/mach-imx/clk-imx51-imx53.c > @@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, > /* move usb phy clk to 24MHz */ > clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); > > + /* move can bus clk to 24MHz */ > + clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); > + > clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); > clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ > clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); > -- Again, CAN is missing on i.MX51, so this should be moved from common_init function. ---
On 11/25/2013 06:27 PM, Alexander Shiyan wrote: >> This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the >> lp_apm clock, which has a rate of 24 MHz. >> >> In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA >> recommented bit rates. Without this patch the CAN peripheral clock on i.MX53 >> has a rate of 66.666 MHz which produces quite large bit rate errors. >> >> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> >> --- >> arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c >> index e349fd5..28f7f3f 100644 >> --- a/arch/arm/mach-imx/clk-imx51-imx53.c >> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c >> @@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, >> /* move usb phy clk to 24MHz */ >> clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); >> >> + /* move can bus clk to 24MHz */ >> + clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); >> + >> clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); >> clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ >> clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); >> -- > > Again, CAN is missing on i.MX51, so this should be moved from common_init function. Doh, will fix. Marc
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index e349fd5..28f7f3f 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, /* move usb phy clk to 24MHz */ clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + /* move can bus clk to 24MHz */ + clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); + clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the lp_apm clock, which has a rate of 24 MHz. In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA recommented bit rates. Without this patch the CAN peripheral clock on i.MX53 has a rate of 66.666 MHz which produces quite large bit rate errors. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++ 1 file changed, 3 insertions(+)