From patchwork Sat Feb 11 17:14:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 140787 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DF7FCB71A5 for ; Sun, 12 Feb 2012 04:17:49 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RwGXo-0003cE-1R; Sat, 11 Feb 2012 17:15:28 +0000 Received: from mail-pz0-f49.google.com ([209.85.210.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RwGXE-0003WU-Lr for linux-arm-kernel@lists.infradead.org; Sat, 11 Feb 2012 17:14:54 +0000 Received: by mail-pz0-f49.google.com with SMTP id p5so3901094dak.36 for ; Sat, 11 Feb 2012 09:14:52 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.210.12 with SMTP id mq12mr28317827pbc.2.1328980492405; Sat, 11 Feb 2012 09:14:52 -0800 (PST) Received: from localhost.localdomain ([108.60.121.130]) by mx.google.com with ESMTPS id 7sm23707230pbw.13.2012.02.11.09.14.50 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 11 Feb 2012 09:14:51 -0800 (PST) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/8] ARM: imx5: adopt generic_chip irq_domain support for tzic Date: Sat, 11 Feb 2012 09:14:27 -0800 Message-Id: <1328980472-11923-4-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328980472-11923-1-git-send-email-shawn.guo@linaro.org> References: <1328980472-11923-1-git-send-email-shawn.guo@linaro.org> X-Gm-Message-State: ALoCoQmB+drbuszs6eSYdY4wpgaPIu72TnoaF0tvnyMc0e8WoAa2WSE9CV9TAdu6UoixcJk8LLQX X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Grant Likely , Thomas Gleixner , Shawn Guo , Sascha Hauer , Rob Herring X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 6 +++++ arch/arm/boot/dts/imx53.dtsi | 6 +++++ arch/arm/mach-mx5/clock-mx51-mx53.c | 4 +- arch/arm/mach-mx5/imx51-dt.c | 8 ------- arch/arm/mach-mx5/imx53-dt.c | 8 ------- arch/arm/plat-mxc/include/mach/common.h | 2 + arch/arm/plat-mxc/tzic.c | 32 ++++++++++++++++-------------- 7 files changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 6663986..a5fda43 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -171,6 +171,12 @@ status = "disabled"; }; + gpt@73fa0000 { + compatible = "fsl,imx51-gpt", "fsl,gpt"; + reg = <0x73fa0000 0x4000>; + interrupts = <39>; + }; + uart1: uart@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 5dd91b9..05e6412 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -173,6 +173,12 @@ status = "disabled"; }; + gpt@53fa0000 { + compatible = "fsl,imx53-gpt", "fsl,gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + }; + uart1: uart@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 4cb2769..c558cb1 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, /* System timer */ mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), - MX51_INT_GPT); + tzic_irq_create_mapping(MX51_INT_GPT)); return 0; } @@ -1630,7 +1630,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, /* System timer */ mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), - MX53_INT_GPT); + tzic_irq_create_mapping(MX53_INT_GPT)); return 0; } diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c index 1e03ef4..45abf11 100644 --- a/arch/arm/mach-mx5/imx51-dt.c +++ b/arch/arm/mach-mx5/imx51-dt.c @@ -44,13 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static int __init imx51_tzic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - static int __init imx51_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { @@ -63,7 +56,6 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np, } static const struct of_device_id imx51_irq_match[] __initconst = { - { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, }, { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, }, { /* sentinel */ } }; diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c index fd5be0f..52efb32 100644 --- a/arch/arm/mach-mx5/imx53-dt.c +++ b/arch/arm/mach-mx5/imx53-dt.c @@ -48,13 +48,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static int __init imx53_tzic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - static int __init imx53_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { @@ -67,7 +60,6 @@ static int __init imx53_gpio_add_irq_domain(struct device_node *np, } static const struct of_device_id imx53_irq_match[] __initconst = { - { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, }, { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, }, { /* sentinel */ } }; diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 1bf0df8..590153c 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -101,6 +101,8 @@ void tzic_handle_irq(struct pt_regs *); #define imx53_handle_irq tzic_handle_irq #define imx6q_handle_irq gic_handle_irq +extern unsigned int tzic_irq_create_mapping(unsigned int hwirq); + extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); #ifdef CONFIG_DEBUG_LL diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 98308ec..69afe59 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +static struct irq_chip_generic *tzic_gc; #define TZIC_NUM_IRQS 128 @@ -77,15 +79,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) static void tzic_irq_suspend(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - int idx = gc->irq_base >> 5; + int idx = d->hwirq / 32; __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); } static void tzic_irq_resume(struct irq_data *d) { - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - int idx = gc->irq_base >> 5; + int idx = d->hwirq / 32; __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), tzic_base + TZIC_WAKEUP0(idx)); @@ -102,18 +103,14 @@ static struct mxc_extra_irq tzic_extra_irq = { #endif }; -static __init void tzic_init_gc(unsigned int irq_start) +static __init void tzic_init_gc(struct irq_chip_generic *gc) { - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - int idx = irq_start >> 5; + struct irq_chip_type *ct = gc->chip_types; + int idx = gc->hwirq_base / 32; - gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, - handle_level_irq); - gc->private = &tzic_extra_irq; + tzic_gc = gc; gc->wake_enabled = IRQ_MSK(32); - ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; @@ -121,8 +118,6 @@ static __init void tzic_init_gc(unsigned int irq_start) ct->chip.irq_resume = tzic_irq_resume; ct->regs.disable = TZIC_ENCLEAR0(idx); ct->regs.enable = TZIC_ENSET0(idx); - - irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); } asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) @@ -175,8 +170,10 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ - for (i = 0; i < TZIC_NUM_IRQS; i += 32) - tzic_init_gc(i); + irq_setup_generic_chip_domain("tzic", + of_find_compatible_node(NULL, NULL, "fsl,tzic"), + 1, 0, tzic_base, handle_level_irq, TZIC_NUM_IRQS, + 0, IRQ_NOREQUEST, 0, tzic_init_gc, &tzic_extra_irq); #ifdef CONFIG_FIQ /* Initialize FIQ */ @@ -205,3 +202,8 @@ int tzic_enable_wake(void) return 0; } + +unsigned int tzic_irq_create_mapping(unsigned int hwirq) +{ + return irq_create_mapping(tzic_gc->domain, hwirq); +}