From patchwork Fri Jan 20 18:43:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 137083 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 767E21007D1 for ; Sat, 21 Jan 2012 05:45:58 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RoJQw-0001S8-0L; Fri, 20 Jan 2012 18:43:30 +0000 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RoJQr-0001RZ-H2 for linux-arm-kernel@lists.infradead.org; Fri, 20 Jan 2012 18:43:26 +0000 Received: from mail215-ch1-R.bigfish.com (10.43.68.249) by CH1EHSOBE006.bigfish.com (10.43.70.56) with Microsoft SMTP Server id 14.1.225.23; Fri, 20 Jan 2012 18:43:21 +0000 Received: from mail215-ch1 (localhost [127.0.0.1]) by mail215-ch1-R.bigfish.com (Postfix) with ESMTP id F13604E04CF; Fri, 20 Jan 2012 18:43:21 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dhc1bhc31hc1ah2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail215-ch1 (localhost.localdomain [127.0.0.1]) by mail215-ch1 (MessageSwitch) id 1327084999808509_27389; Fri, 20 Jan 2012 18:43:19 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.253]) by mail215-ch1.bigfish.com (Postfix) with ESMTP id BEA435C004B; Fri, 20 Jan 2012 18:43:19 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 20 Jan 2012 18:43:18 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Fri, 20 Jan 2012 12:43:20 -0600 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.240.144]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id q0KIhDnu002582; Fri, 20 Jan 2012 12:43:19 -0600 (CST) From: Fabio Estevam To: Subject: [PATCH 3/3] ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI Date: Fri, 20 Jan 2012 16:43:10 -0200 Message-ID: <1327084990-25402-3-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1327084990-25402-1-git-send-email-fabio.estevam@freescale.com> References: <1327084990-25402-1-git-send-email-fabio.estevam@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.183 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Fabio Estevam , benoit.thebaudeau@advansee.com, eric@eukrea.com, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The LPM field of register CCMR is used to select the mode that the processor will run when it goes to WFI. When mx31 enters in WFI mode the LPM field is at its reset value of 0, which configures the mx31 to enter in "wait mode". On mx35, the LPM field on mx35 is also at 0 after reset, which corresponds to "run mode" instead of "wait mode". Instead of relying on the reset value of LPM to set the low power mode for WFI, configure mx31 and mx35 to run in "wait mode" Reported-by: Benoit Thebaudeau Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/Makefile | 4 +- arch/arm/mach-imx/crmregs-imx3.h | 1 + arch/arm/mach-imx/mm-imx3.c | 4 ++- arch/arm/mach-imx/pm-imx3.c | 36 +++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/common.h | 8 +++++++ 5 files changed, 50 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-imx/pm-imx3.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 88531b6..2dd4af6 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o -obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o -obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o +obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o +obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h index d7691e2..b4d2305 100644 --- a/arch/arm/mach-imx/crmregs-imx3.h +++ b/arch/arm/mach-imx/crmregs-imx3.h @@ -77,6 +77,7 @@ MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)) #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_LPM_WAIT (cpu_is_mx35() ? (0x1 << 14) : 0) #define MXC_CCM_CCMR_FIRS_OFFSET 11 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) #define MXC_CCM_CCMR_UPE (1 << 9) diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 3555e0b..dda8f25 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -34,7 +34,8 @@ static void imx3_idle(void) { unsigned long reg = 0; - if (!need_resched()) + if (!need_resched()) { + mx3_cpu_lp_set(MX3_WAIT); __asm__ __volatile__( /* disable I and D cache */ "mrc p15, 0, %0, c1, c0, 0\n" @@ -58,6 +59,7 @@ static void imx3_idle(void) "orr %0, %0, #0x00000004\n" "mcr p15, 0, %0, c1, c0, 0\n" : "=r" (reg)); + } local_irq_enable(); } diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c new file mode 100644 index 0000000..ae216db --- /dev/null +++ b/arch/arm/mach-imx/pm-imx3.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include "crmregs-imx3.h" + +/* + * Set cpu low power mode before WFI instruction. This function is called + * mx3 because it can be used for mx31 and mx35. + * Currently only WAIT_MODE is supported. + */ +void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) +{ + int reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + + switch (mode) { + case MX3_WAIT: + reg |= MXC_CCM_CCMR_LPM_WAIT; + __raw_writel(reg, MXC_CCM_CCMR); + break; + default: + pr_err("Unknown cpu power mode: %d\n", mode); + return; + } +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 1bf0df8..06595a3 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -84,6 +84,14 @@ enum mxc_cpu_pwr_mode { STOP_POWER_OFF, /* STOP + SRPG */ }; +enum mx3_cpu_pwr_mode { + MX3_RUN, + MX3_WAIT, + MX3_DOZE, + MX3_SLEEP, +}; + +extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); extern void imx_print_silicon_rev(const char *cpu, int srev);