From patchwork Fri Jan 6 15:39:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 134667 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 288E5B6FB6 for ; Sat, 7 Jan 2012 02:33:30 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RjBjj-0007Q6-LR; Fri, 06 Jan 2012 15:29:43 +0000 Received: from mail-gx0-f177.google.com ([209.85.161.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RjBjc-0007PW-C6 for linux-arm-kernel@lists.infradead.org; Fri, 06 Jan 2012 15:29:37 +0000 Received: by ggnp4 with SMTP id p4so783077ggn.36 for ; Fri, 06 Jan 2012 07:29:35 -0800 (PST) Received: by 10.50.214.38 with SMTP id nx6mr8161867igc.19.1325863775286; Fri, 06 Jan 2012 07:29:35 -0800 (PST) Received: from localhost.localdomain ([114.216.146.193]) by mx.google.com with ESMTPS id va6sm31070148igc.6.2012.01.06.07.29.30 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 Jan 2012 07:29:34 -0800 (PST) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] ARM: mxs: detect SoC by checking CHIPID register Date: Fri, 6 Jan 2012 23:39:25 +0800 Message-Id: <1325864366-17995-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1325864366-17995-1-git-send-email-shawn.guo@linaro.org> References: <1325864366-17995-1-git-send-email-shawn.guo@linaro.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.161.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo , Wolfram Sang , Lauri Hintsala X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Both imx23 and imx28 have CHIPID register at address 0x8001c310, which can be used to identify the SoC. This patch changes cpu_is_xxx and __arch_decomp_setup to use this CHIPID register than machine type to detect the chip between imx23 and imx28, so that we do not need to change these functions whenever a new board/machine gets added. Suggested-by: Wolfram Sang Signed-off-by: Shawn Guo Acked-by: Wolfram Sang Acked-by: Marek Vasut --- arch/arm/mach-mxs/include/mach/digctl.h | 1 + arch/arm/mach-mxs/include/mach/mxs.h | 29 ++++++++++++++------------ arch/arm/mach-mxs/include/mach/uncompress.h | 13 +++++------ 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h index 49a888c..1796406 100644 --- a/arch/arm/mach-mxs/include/mach/digctl.h +++ b/arch/arm/mach-mxs/include/mach/digctl.h @@ -18,4 +18,5 @@ #define HW_DIGCTL_CTRL 0x0 #define BP_DIGCTL_CTRL_SAIF_CLKMUX 10 #define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10) +#define HW_DIGCTL_CHIPID 0x310 #endif diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index bde5f66..7d4fb6d 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -23,22 +23,10 @@ #include #endif #include +#include #include /* - * MXS CPU types - */ -#define cpu_is_mx23() ( \ - machine_is_mx23evk() || \ - machine_is_stmp378x() || \ - 0) -#define cpu_is_mx28() ( \ - machine_is_mx28evk() || \ - machine_is_m28evk() || \ - machine_is_tx28() || \ - 0) - -/* * IO addresses common to MXS-based */ #define MXS_IO_BASE_ADDR 0x80000000 @@ -109,6 +97,21 @@ static inline void __mxs_togl(u32 mask, void __iomem *reg) { __raw_writel(mask, reg + MXS_TOG_ADDR); } + +/* + * MXS CPU types + */ +#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID) + +static inline int cpu_is_mx23(void) +{ + return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780); +} + +static inline int cpu_is_mx28(void) +{ + return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800); +} #endif #endif /* __MACH_MXS_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index 6777674..ef28114 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -18,8 +18,6 @@ #ifndef __MACH_MXS_UNCOMPRESS_H__ #define __MACH_MXS_UNCOMPRESS_H__ -#include - unsigned long mxs_duart_base; #define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) @@ -55,16 +53,17 @@ static inline void flush(void) #define MX23_DUART_BASE_ADDR 0x80070000 #define MX28_DUART_BASE_ADDR 0x80074000 +#define MXS_DIGCTL_CHIPID 0x8001c310 static inline void __arch_decomp_setup(unsigned long arch_id) { - switch (arch_id) { - case MACH_TYPE_MX23EVK: + u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16; + + switch (chipid) { + case 0x3780: mxs_duart_base = MX23_DUART_BASE_ADDR; break; - case MACH_TYPE_MX28EVK: - case MACH_TYPE_M28EVK: - case MACH_TYPE_TX28: + case 0x2800: mxs_duart_base = MX28_DUART_BASE_ADDR; break; default: