| Message ID | 20220111212606.2072669-1-Mr.Bossman075@gmail.com |
|---|---|
| Headers | show |
| Series | Add initial support for the i.MXRTxxxx SoC family starting from i.IMXRT1050 SoC. | expand |
This patchset contains: - i.MXRT10xx family infrastructure - i.MXRT1050 pinctrl driver adaption - i.MXRT1050 clock driver adaption - i.MXRT1050 sd-card driver adaption - i.MXRT1050 uart driver adaption - i.MXRT1050-evk basic support The i.MXRTxxxx family that could have support by Linux actually spreads from i.MXRT1020 to i.MXRT1170 with the first one supporting 1 USB OTG & 100M ethernet with a cortex-M7@500Mhz up to the latter with i.MXRT1170 with cortex-M7@1Ghz and cortex-M4@400Mhz, 2MB of internal SRAM, 2D GPU, 2x 1Gb and 1x 100Mb ENET. The i.MXRT family is NXP's answer to STM32F7XX, as it uses only simple SDRAM, it gives the chance of a 4 or less layer PCBs. Seeing that these chips are comparable to the STM32F7XXs which have linux ported to them it seems reasonable to add support for them. Giving Linux support to this family should ease the development process, instead of using a RTOS they could use Embedded Linux allowing for more portability, ease of design and will broaden the scope of people using embedded linux. The EVK has very little SDRAM, generally 32MB starting from i.MXRT1020(the lowest P/N), although the i.MXRT1160/70 provide instead 64MB of SDRAM for more functionality. At the moment we do not support XIP for either u-boot or Linux but it should be done in the future. XIP will also save SDRAM. Another interesting fact is the amount of internal SRAM, as the P/N increases the SRAM will reach up to 2MB(some could be for cache and some would be for video). Also, some parts have embed flash of 4MB that can be used for u-boot/Linux, if both correctly sized it will leave the SDRAM free. External flash can be Quad SPI and HyperFlash, so throughput would be decent. The i.MXRT11xx series supports MIPI interface too. The family in general provide CAN bus, audio I/O, 1 or more USB(otg/host), 1 or more 100Mb/1Gb ethernet, camera interface, sd-card. All this can be used for simple GUIs, web-servers, point-of-sale stations, etc. Giulio Benetti (4): ARM: imx: Add initial support for i.MXRT10xx family dt-bindings: imx: Add clock binding for i.MXRT1050 ARM: dts: imx: Add i.MXRT1050-EVK support ARM: imxrt_defconfig: Add i.MXRT family defconfig Jesse Taube (3): ARM: dts: imxrt1050-pinfunc: Add pinctrl binding header dt-bindings: clock: imx: Add documentation for i.MXRT1050 clock clk: imx: Add initial support for i.MXRT1050 clock driver .../bindings/clock/imxrt1050-clock.yaml | 67 ++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imxrt1050-evk.dts | 72 ++ arch/arm/boot/dts/imxrt1050-pinfunc.h | 993 ++++++++++++++++++ arch/arm/boot/dts/imxrt1050.dtsi | 160 +++ arch/arm/configs/imxrt_defconfig | 35 + arch/arm/mach-imx/Kconfig | 7 + arch/arm/mach-imx/Makefile | 2 + arch/arm/mach-imx/mach-imxrt.c | 19 + drivers/clk/imx/Kconfig | 7 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imxrt1050.c | 168 +++ include/dt-bindings/clock/imxrt1050-clock.h | 72 ++ 13 files changed, 1605 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts create mode 100644 arch/arm/boot/dts/imxrt1050-pinfunc.h create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi create mode 100644 arch/arm/configs/imxrt_defconfig create mode 100644 arch/arm/mach-imx/mach-imxrt.c create mode 100644 drivers/clk/imx/clk-imxrt1050.c create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
On 1/11/22 16:25, Jesse Taube wrote: > This patchset contains: > - i.MXRT10xx family infrastructure > - i.MXRT1050 pinctrl driver adaption > - i.MXRT1050 clock driver adaption > - i.MXRT1050 sd-card driver adaption > - i.MXRT1050 uart driver adaption > - i.MXRT1050-evk basic support > > The i.MXRTxxxx family that could have support by Linux actually spreads > from i.MXRT1020 to i.MXRT1170 with the first one supporting 1 USB OTG & > 100M ethernet with a cortex-M7@500Mhz up to the latter with i.MXRT1170 > with cortex-M7@1Ghz and cortex-M4@400Mhz, 2MB of internal SRAM, 2D GPU, > 2x 1Gb and 1x 100Mb ENET. The i.MXRT family is NXP's answer to > STM32F7XX, as it uses only simple SDRAM, it gives the chance of a 4 or > less layer PCBs. Seeing that these chips are comparable to the > STM32F7XXs which have linux ported to them it seems reasonable to add > support for them. > > Giving Linux support to this family should ease the development process, > instead of using a RTOS they could use Embedded Linux allowing for more > portability, ease of design and will broaden the scope of people using > embedded linux. > > The EVK has very little SDRAM, generally 32MB starting from > i.MXRT1020(the lowest P/N), although the i.MXRT1160/70 provide instead > 64MB of SDRAM for more functionality. > > At the moment we do not support XIP for either u-boot or Linux but it > should be done in the future. XIP will also save SDRAM. > > Another interesting fact is the amount of internal SRAM, as the P/N > increases the SRAM will reach up to 2MB(some could be for cache and > some would be for video). > > Also, some parts have embed flash of 4MB that can be used for > u-boot/Linux, if both correctly sized it will leave the SDRAM free. > > External flash can be Quad SPI and HyperFlash, so throughput would be > decent. > > The i.MXRT11xx series supports MIPI interface too. > > The family in general provide CAN bus, audio I/O, 1 or more > USB(otg/host), 1 or more 100Mb/1Gb ethernet, camera interface, sd-card. > > All this can be used for simple GUIs, web-servers, point-of-sale > stations, etc. > > > Giulio Benetti (4): > ARM: imx: Add initial support for i.MXRT10xx family > dt-bindings: imx: Add clock binding for i.MXRT1050 > ARM: dts: imx: Add i.MXRT1050-EVK support > ARM: imxrt_defconfig: Add i.MXRT family defconfig > > Jesse Taube (3): > ARM: dts: imxrt1050-pinfunc: Add pinctrl binding header > dt-bindings: clock: imx: Add documentation for i.MXRT1050 clock > clk: imx: Add initial support for i.MXRT1050 clock driver > > .../bindings/clock/imxrt1050-clock.yaml | 67 ++ > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imxrt1050-evk.dts | 72 ++ > arch/arm/boot/dts/imxrt1050-pinfunc.h | 993 ++++++++++++++++++ > arch/arm/boot/dts/imxrt1050.dtsi | 160 +++ > arch/arm/configs/imxrt_defconfig | 35 + > arch/arm/mach-imx/Kconfig | 7 + > arch/arm/mach-imx/Makefile | 2 + > arch/arm/mach-imx/mach-imxrt.c | 19 + > drivers/clk/imx/Kconfig | 7 + > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-imxrt1050.c | 168 +++ > include/dt-bindings/clock/imxrt1050-clock.h | 72 ++ > 13 files changed, 1605 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml > create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts > create mode 100644 arch/arm/boot/dts/imxrt1050-pinfunc.h > create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi > create mode 100644 arch/arm/configs/imxrt_defconfig > create mode 100644 arch/arm/mach-imx/mach-imxrt.c > create mode 100644 drivers/clk/imx/clk-imxrt1050.c > create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h > Oh No! I'm very sorry I sent v8 under the wrong version number. I sent it again... Sincerely, Jesse Taube
Quoting Jesse Taube (2022-01-11 13:54:11) > From: Giulio Benetti <giulio.benetti@benettiengineering.com> > > Add the clock binding doc for i.MXRT1050. > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > [Giulio: added all clocks up to IMXRT1050_CLK_USBOH3] > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: added clocks from IMXRT1050_CLK_IPG_PDOF to > IMXRT1050_CLK_DMA_MUX and moved IMXRT1050_CLK_END on] > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
Quoting Jesse Taube (2022-01-11 13:54:12) > From: Jesse Taube <mr.bossman075@gmail.com> > > Add DT binding documentation for i.MXRT1050 clock driver. > > Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Quoting Jesse Taube (2022-01-11 13:54:13) > Add clock driver support for i.MXRT1050. > > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > Suggested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
On 22-01-11 16:54:11, Jesse Taube wrote: > From: Giulio Benetti <giulio.benetti@benettiengineering.com> > > Add the clock binding doc for i.MXRT1050. > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > [Giulio: added all clocks up to IMXRT1050_CLK_USBOH3] > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: added clocks from IMXRT1050_CLK_IPG_PDOF to > IMXRT1050_CLK_DMA_MUX and moved IMXRT1050_CLK_END on] Applied, thanks. > --- > V1->V2: > * Nothing done > V2->V3: > * Added GPT binding > V3->V4: > * Change License to MIT or GPL-2 > V4->V5: > * Nothing done > V5->V6: > * Nothing done > V6->V7: > * Fix typo in numbering > * Remove GPT > V7->V8: > * Nothing done > --- > include/dt-bindings/clock/imxrt1050-clock.h | 72 +++++++++++++++++++++ > 1 file changed, 72 insertions(+) > create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h > > diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h > new file mode 100644 > index 000000000000..93bef0832d16 > --- /dev/null > +++ b/include/dt-bindings/clock/imxrt1050-clock.h > @@ -0,0 +1,72 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ > +/* > + * Copyright(C) 2019 > + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H > +#define __DT_BINDINGS_CLOCK_IMXRT1050_H > + > +#define IMXRT1050_CLK_DUMMY 0 > +#define IMXRT1050_CLK_CKIL 1 > +#define IMXRT1050_CLK_CKIH 2 > +#define IMXRT1050_CLK_OSC 3 > +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 > +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 > +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 > +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 > +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 > +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 > +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 > +#define IMXRT1050_CLK_PLL2_198M 11 > +#define IMXRT1050_CLK_PLL3_120M 12 > +#define IMXRT1050_CLK_PLL3_80M 13 > +#define IMXRT1050_CLK_PLL3_60M 14 > +#define IMXRT1050_CLK_PLL1_BYPASS 15 > +#define IMXRT1050_CLK_PLL2_BYPASS 16 > +#define IMXRT1050_CLK_PLL3_BYPASS 17 > +#define IMXRT1050_CLK_PLL5_BYPASS 19 > +#define IMXRT1050_CLK_PLL1_REF_SEL 20 > +#define IMXRT1050_CLK_PLL2_REF_SEL 21 > +#define IMXRT1050_CLK_PLL3_REF_SEL 22 > +#define IMXRT1050_CLK_PLL5_REF_SEL 23 > +#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 > +#define IMXRT1050_CLK_PERIPH_SEL 25 > +#define IMXRT1050_CLK_SEMC_ALT_SEL 26 > +#define IMXRT1050_CLK_SEMC_SEL 27 > +#define IMXRT1050_CLK_USDHC1_SEL 28 > +#define IMXRT1050_CLK_USDHC2_SEL 29 > +#define IMXRT1050_CLK_LPUART_SEL 30 > +#define IMXRT1050_CLK_LCDIF_SEL 31 > +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 > +#define IMXRT1050_CLK_VIDEO_DIV 33 > +#define IMXRT1050_CLK_ARM_PODF 34 > +#define IMXRT1050_CLK_LPUART_PODF 35 > +#define IMXRT1050_CLK_USDHC1_PODF 36 > +#define IMXRT1050_CLK_USDHC2_PODF 37 > +#define IMXRT1050_CLK_SEMC_PODF 38 > +#define IMXRT1050_CLK_AHB_PODF 39 > +#define IMXRT1050_CLK_LCDIF_PRED 40 > +#define IMXRT1050_CLK_LCDIF_PODF 41 > +#define IMXRT1050_CLK_USDHC1 42 > +#define IMXRT1050_CLK_USDHC2 43 > +#define IMXRT1050_CLK_LPUART1 44 > +#define IMXRT1050_CLK_SEMC 45 > +#define IMXRT1050_CLK_LCDIF_APB 46 > +#define IMXRT1050_CLK_PLL1_ARM 47 > +#define IMXRT1050_CLK_PLL2_SYS 48 > +#define IMXRT1050_CLK_PLL3_USB_OTG 49 > +#define IMXRT1050_CLK_PLL4_AUDIO 50 > +#define IMXRT1050_CLK_PLL5_VIDEO 51 > +#define IMXRT1050_CLK_PLL6_ENET 52 > +#define IMXRT1050_CLK_PLL7_USB_HOST 53 > +#define IMXRT1050_CLK_LCDIF_PIX 54 > +#define IMXRT1050_CLK_USBOH3 55 > +#define IMXRT1050_CLK_IPG_PDOF 56 > +#define IMXRT1050_CLK_PER_CLK_SEL 57 > +#define IMXRT1050_CLK_PER_PDOF 58 > +#define IMXRT1050_CLK_DMA 59 > +#define IMXRT1050_CLK_DMA_MUX 60 > +#define IMXRT1050_CLK_END 61 > + > +#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ > -- > 2.34.1 >
On 22-01-11 16:54:12, Jesse Taube wrote: > From: Jesse Taube <mr.bossman075@gmail.com> > > Add DT binding documentation for i.MXRT1050 clock driver. > > Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Applied, thanks. > --- > V1->V2: > * Replace macros with values > V2->V3: > * Remove anatop > * Use lpuart not gpt > * include imxrt1050-clock.h > * 2 space tabs to 4 > * Remove oneOf enum > * Change maxItems to 2 > V3->V4: > * Nothing done > V4->V5: > * Remove extra newline > * Rename ccm to clock-controller > * Change minItems to const > * Change minItems to description > * Rename file to add 1050 > * Change commit description to just 1050 > V5->V6: > * Add maxItems for clocks description > V6->V7: > * Nothing done > V7->V8: > * Nothing done > --- > .../bindings/clock/imxrt1050-clock.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml b/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml > new file mode 100644 > index 000000000000..35fd08c143f4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Clock bindings for Freescale i.MXRT > + > +maintainers: > + - Giulio Benetti <giulio.benetti@benettiengineering.com> > + - Jesse Taube <Mr.Bossman075@gmail.com> > + > +description: | > + The clock consumer should specify the desired clock by having the clock > + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h > + for the full list of i.MXRT clock IDs. > + > +properties: > + compatible: > + const: fsl,imxrt1050-ccm > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 2 > + > + clocks: > + description: 24m osc > + maxItems: 1 > + > + clock-names: > + const: osc > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imxrt1050-clock.h> > + > + clks: clock-controller@400fc000 { > + compatible = "fsl,imxrt1050-ccm"; > + reg = <0x400fc000 0x4000>; > + interrupts = <95>, <96>; > + clocks = <&osc>; > + clock-names = "osc"; > + #clock-cells = <1>; > + }; > + > + lpuart1: serial@40184000 { > + compatible = "fsl,imxrt1050-lpuart"; > + reg = <0x40184000 0x4000>; > + interrupts = <20>; > + clocks = <&clks IMXRT1050_CLK_LPUART1>; > + clock-names = "ipg"; > + }; > -- > 2.34.1 >
On 22-01-11 16:54:13, Jesse Taube wrote: > Add clock driver support for i.MXRT1050. > > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > Suggested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Applied, thanks. > --- > V1->V2: > * Kconfig: Add new line > * clk-imxrt.c: Remove unused const > * clk-imxrt.c: Remove set parents > * clk-imxrt.c: Use fsl,imxrt-anatop for anatop base address > V2->V3: > * Remove unused ANATOP_BASE_ADDR > * Move to hw API > * Add GPT's own clock > * Add SEMC clocks to set muxing to CRITICAL > V3->V4: > * Rename clk-imxrt.c to clk-imxrt1050.c > * Rename CONFIG_CLK_IMXRT to CONFIG_CLK_IMXRT1050 > * Make CONFIG_CLK_IMXRT1050 selectable > V4->V5: > * Move to platform driver > V5->V6: > * Remove "fsl" from platform driver name > V6->V7: > * Remove GPT > * Remove of_match_ptr > V7->V8: > * Add help message > * Change to config to tristate > * Fix Makefile ordering > * Remove unused inlcude > * Remove imxrt_clocks_common_init > --- > drivers/clk/imx/Kconfig | 7 ++ > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-imxrt1050.c | 168 ++++++++++++++++++++++++++++++++ > 3 files changed, 176 insertions(+) > create mode 100644 drivers/clk/imx/clk-imxrt1050.c > > diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig > index c08edbd04d22..45641b8bdc50 100644 > --- a/drivers/clk/imx/Kconfig > +++ b/drivers/clk/imx/Kconfig > @@ -105,3 +105,10 @@ config CLK_IMX8ULP > select MXC_CLK > help > Build the driver for i.MX8ULP CCM Clock Driver > + > +config CLK_IMXRT1050 > + tristate "IMXRT1050 CCM Clock Driver" > + depends on SOC_IMXRT > + select MXC_CLK > + help > + Build the driver for i.MXRT1050 CCM Clock Driver > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index b5e040026dfb..1e13c5cb37d9 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -46,4 +46,5 @@ obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o > obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o > obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o > obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o > +obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o > obj-$(CONFIG_CLK_VF610) += clk-vf610.o > diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c > new file mode 100644 > index 000000000000..9539d35588ee > --- /dev/null > +++ b/drivers/clk/imx/clk-imxrt1050.c > @@ -0,0 +1,168 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (C) 2021 > + * Author(s): > + * Jesse Taube <Mr.Bossman075@gmail.com> > + * Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > +#include <linux/clk.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <dt-bindings/clock/imxrt1050-clock.h> > + > +#include "clk.h" > + > +static const char * const pll_ref_sels[] = {"osc", "dummy", }; > +static const char * const per_sels[] = {"ipg_pdof", "osc", }; > +static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; > +static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; > +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; > +static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; > +static const char *const pre_periph_sels[] = { > + "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; > +static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; > +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; > +static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; > +static const char *const lcdif_sels[] = { > + "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", > + "pll2_pfd1_594m", "pll3_pfd1_664_62m", }; > +static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; > +static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; > + > +static struct clk_hw **hws; > +static struct clk_hw_onecell_data *clk_hw_data; > + > +static int imxrt1050_clocks_probe(struct platform_device *pdev) > +{ > + void __iomem *ccm_base; > + void __iomem *pll_base; > + struct device *dev = &pdev->dev; > + struct device_node *np = dev->of_node; > + struct device_node *anp; > + int ret; > + > + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, > + IMXRT1050_CLK_END), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) > + return -ENOMEM; > + > + clk_hw_data->num = IMXRT1050_CLK_END; > + hws = clk_hw_data->hws; > + > + hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc"); > + > + anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop"); > + pll_base = of_iomap(anp, 0); > + of_node_put(anp); > + if (WARN_ON(!pll_base)) > + return -ENOMEM; > + > + /* Anatop clocks */ > + hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL); > + > + hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel", > + pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel", > + pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel", > + pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel", > + pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + > + hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm", > + "pll1_arm_ref_sel", pll_base + 0x0, 0x7f); > + hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", > + "pll2_sys_ref_sel", pll_base + 0x30, 0x1); > + hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", > + "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1); > + hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video", > + "pll5_video_ref_sel", pll_base + 0xa0, 0x7f); > + > + /* PLL bypass out */ > + hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1, > + pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); > + hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1, > + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); > + hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1, > + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); > + hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1, > + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); > + > + hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel", > + "pll5_video", pll_base + 0xa0, 19, 2); > + hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div", > + "video_post_div_sel", pll_base + 0x170, 30, 2); > + > + hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); > + > + hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0); > + hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1); > + hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2); > + hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1); > + hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3); > + > + /* CCM clocks */ > + ccm_base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(ccm_base))) > + return PTR_ERR(ccm_base); > + > + hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3); > + hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2, > + pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); > + hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1, > + periph_sels, ARRAY_SIZE(periph_sels)); > + hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1, > + usdhc_sels, ARRAY_SIZE(usdhc_sels)); > + hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1, > + usdhc_sels, ARRAY_SIZE(usdhc_sels)); > + hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1, > + lpuart_sels, ARRAY_SIZE(lpuart_sels)); > + hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3, > + lcdif_sels, ARRAY_SIZE(lcdif_sels)); > + hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1, > + per_sels, ARRAY_SIZE(per_sels)); > + hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1, > + semc_alt_sels, ARRAY_SIZE(semc_alt_sels)); > + hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1, > + semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL); > + > + hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3); > + hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2); > + hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5); > + > + hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3); > + hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3); > + hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6); > + hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3); > + hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3); > + > + hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); > + hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); > + hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); > + hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); > + hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); > + hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); > + imx_check_clk_hws(hws, IMXRT1050_CLK_END); > + > + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); > + if (ret < 0) { > + dev_err(dev, "Failed to register clks for i.MXRT1050.\n"); > + imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END); > + } > + return ret; > +} > +static const struct of_device_id imxrt1050_clk_of_match[] = { > + { .compatible = "fsl,imxrt1050-ccm" }, > + { /* Sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match); > + > +static struct platform_driver imxrt1050_clk_driver = { > + .probe = imxrt1050_clocks_probe, > + .driver = { > + .name = "imxrt1050-ccm", > + .of_match_table = imxrt1050_clk_of_match, > + }, > +}; > +module_platform_driver(imxrt1050_clk_driver); > -- > 2.34.1 >
On Tue, 11 Jan 2022 16:54:10 -0500, Jesse Taube wrote: > From: Jesse Taube <mr.bossman075@gmail.com> > > Add binding header for i.MXRT1050 pinctrl device tree. > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: move pinfunc from dt-bindings to dts folder] > --- > V1->V2: > * Move pinfunc from dt-binding to dts > * Change subject and description > * Change licence to "GPL-2.0+ OR MIT" > V2->V3: > * Change License comment style > V3->V4: > * Nothing done > V4->V5: > * Nothing done > V5->V6: > * Nothing done > V6->V7: > * Nothing done > V7->V8: > * Nothing done > --- > arch/arm/boot/dts/imxrt1050-pinfunc.h | 993 ++++++++++++++++++++++++++ > 1 file changed, 993 insertions(+) > create mode 100644 arch/arm/boot/dts/imxrt1050-pinfunc.h > Acked-by: Rob Herring <robh@kernel.org>
On Tue, Jan 11, 2022 at 04:54:10PM -0500, Jesse Taube wrote: > From: Jesse Taube <mr.bossman075@gmail.com> > > Add binding header for i.MXRT1050 pinctrl device tree. > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: move pinfunc from dt-bindings to dts folder] Applied, thanks!
On Tue, Jan 11, 2022 at 04:54:14PM -0500, Jesse Taube wrote: > From: Giulio Benetti <giulio.benetti@benettiengineering.com> > > The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid > evaluation of the i.MXRT, which features NXP's implementation of the Arm > Cortex-M7 core. > > The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, > USB 2.0 OTG. > > This patch aims to support the preliminary booting up features > as follows: > GPIO > LPUART > SD/MMC > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] > --- > V1->V2: > * dtsi: Add clock parent definitions > * dtsi: Change hex values to lowercase > * dtsi: Move anatop definition from driver > * dts: Remove unused pin controll (semc) > * dts: Use moved pin controll header > * Move aliases from dtsi to dts > * Change commit description > * Change licence to "GPL-2.0+ OR MIT" > V2->V3: > * Remove bootargs, comments, unused container > * Remove unnecessary new lines > * Rename imxrt to imxrt1050 for seiral and mmc > * GPT uses own clock > * fix memory@0 > * Change GPT compatible handles > V3->V4: > * Remove "fsl,imx-osc" > * Add space on serial compatible > * Change "iomuxc@" to "pinctrl@" > * Change "ccm@" to "clock-controller@" > * Change "fsl,imxrt-gpio" to "fsl,imxrt1050-gpio" > V4->V5: > * Nothing done > V5->V6: > * Nothing done > V6->V7: > * Add fixed clock for GPT > * Fix lpuart compatible > * Add usdhc compatible > V7->V8: > * Nothing done > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imxrt1050-evk.dts | 72 +++++++++++++ > arch/arm/boot/dts/imxrt1050.dtsi | 160 ++++++++++++++++++++++++++++ > 3 files changed, 234 insertions(+) > create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts > create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 0de64f237cd8..07acd6189cae 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -723,6 +723,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ > dtb-$(CONFIG_SOC_IMX7ULP) += \ > imx7ulp-com.dtb \ > imx7ulp-evk.dtb > +dtb-$(CONFIG_SOC_IMXRT) += \ > + imxrt1050-evk.dtb > dtb-$(CONFIG_SOC_LS1021A) += \ > ls1021a-moxa-uc-8410a.dtb \ > ls1021a-qds.dtb \ > diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts > new file mode 100644 > index 000000000000..6a9c10decf52 > --- /dev/null > +++ b/arch/arm/boot/dts/imxrt1050-evk.dts > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 > + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > + > +/dts-v1/; > +#include "imxrt1050.dtsi" > +#include "imxrt1050-pinfunc.h" > + > +/ { > + model = "NXP IMXRT1050-evk board"; > + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + aliases { > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + mmc0 = &usdhc1; > + serial0 = &lpuart1; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x2000000>; > + }; > +}; > + > +&lpuart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart1>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl_lpuart1: lpuart1grp { > + fsl,pins = < > + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 > + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 > + >; > + }; > + > + pinctrl_usdhc0: usdhc0grp { > + fsl,pins = < > + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 > + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 > + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 > + >; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0>; > + pinctrl-2 = <&pinctrl_usdhc0>; > + pinctrl-3 = <&pinctrl_usdhc0>; > + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi > new file mode 100644 > index 000000000000..77b911b06041 > --- /dev/null > +++ b/arch/arm/boot/dts/imxrt1050.dtsi > @@ -0,0 +1,160 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 > + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > + > +#include "armv7-m.dtsi" > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/imxrt1050-clock.h> As this introduces a cross tree dependency (between clk and imx), we may need to wait for clock change land first. Shawn > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + clocks { > + osc: osc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + > + osc3M: osc3M { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <3000000>; > + }; > + }; > + > + soc { > + lpuart1: serial@40184000 { > + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; > + reg = <0x40184000 0x4000>; > + interrupts = <20>; > + clocks = <&clks IMXRT1050_CLK_LPUART1>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + iomuxc: pinctrl@401f8000 { > + compatible = "fsl,imxrt1050-iomuxc"; > + reg = <0x401f8000 0x4000>; > + fsl,mux_mask = <0x7>; > + }; > + > + anatop: anatop@400d8000 { > + compatible = "fsl,imxrt-anatop"; > + reg = <0x400d8000 0x4000>; > + }; > + > + clks: clock-controller@400fc000 { > + compatible = "fsl,imxrt1050-ccm"; > + reg = <0x400fc000 0x4000>; > + interrupts = <95>, <96>; > + clocks = <&osc>; > + clock-names = "osc"; > + #clock-cells = <1>; > + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, > + <&clks IMXRT1050_CLK_PLL1_BYPASS>, > + <&clks IMXRT1050_CLK_PLL2_BYPASS>, > + <&clks IMXRT1050_CLK_PLL3_BYPASS>, > + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, > + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; > + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, > + <&clks IMXRT1050_CLK_PLL1_ARM>, > + <&clks IMXRT1050_CLK_PLL2_SYS>, > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, > + <&clks IMXRT1050_CLK_PLL2_SYS>; > + }; > + > + edma1: dma-controller@400e8000 { > + #dma-cells = <2>; > + compatible = "fsl,imx7ulp-edma"; > + reg = <0x400e8000 0x4000>, > + <0x400ec000 0x4000>; > + dma-channels = <32>; > + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, > + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; > + clock-names = "dma", "dmamux0"; > + clocks = <&clks IMXRT1050_CLK_DMA>, > + <&clks IMXRT1050_CLK_DMA_MUX>; > + }; > + > + usdhc1: mmc@402c0000 { > + compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; > + reg = <0x402c0000 0x4000>; > + interrupts = <110>; > + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, > + <&clks IMXRT1050_CLK_OSC>, > + <&clks IMXRT1050_CLK_USDHC1>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + fsl,wp-controller; > + no-1-8-v; > + max-frequency = <4000000>; > + fsl,tuning-start-tap = <20>; > + fsl,tuning-step= <2>; > + status = "disabled"; > + }; > + > + gpio1: gpio@401b8000 { > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; > + reg = <0x401b8000 0x4000>; > + interrupts = <80>, <81>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio@401bc000 { > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; > + reg = <0x401bc000 0x4000>; > + interrupts = <82>, <83>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio@401c0000 { > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; > + reg = <0x401c0000 0x4000>; > + interrupts = <84>, <85>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio4: gpio@401c4000 { > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; > + reg = <0x401c4000 0x4000>; > + interrupts = <86>, <87>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio5: gpio@400c0000 { > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; > + reg = <0x400c0000 0x4000>; > + interrupts = <88>, <89>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpt: timer@401ec000 { > + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; > + reg = <0x401ec000 0x4000>; > + interrupts = <100>; > + clocks = <&osc3M>; > + clock-names = "per"; > + }; > + }; > +}; > -- > 2.34.1 >