Message ID | 1450244630-10065-2-git-send-email-Yuantian.Tang@freescale.com |
---|---|
State | Not Applicable |
Delegated to: | David Miller |
Headers | show |
On Wed, Dec 16, 2015 at 01:43:50PM +0800, Yuantian.Tang@freescale.com wrote: > From: Tang Yuantian <Yuantian.Tang@freescale.com> > > The PTC[RXWM] sets the watermark value for Rx FIFO. The default > value 0x20 might be insufficient for some hard drives. If the > watermark value is too small, a single-cycle overflow may occur > and is reported as a CRC or internal error in the PxSERR register. > Updated the value to 0x29 according to the validation test. > All LS platforms are affected. > > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Applied 1-2 to libata/for-4.5. Thanks.
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index 4d613f8..256d911 100644 --- a/drivers/ata/ahci_qoriq.c +++ b/drivers/ata/ahci_qoriq.c @@ -38,7 +38,7 @@ #define AHCI_PORT_PHY_3_CFG 0x0e081004 #define AHCI_PORT_PHY_4_CFG 0x00480811 #define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define LS1043A_PORT_PHY2 0x28184d1f #define LS1043A_PORT_PHY3 0x0e081509 @@ -169,6 +169,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) case AHCI_LS2080A: writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); break; }