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Wed, 4 Nov 2020 15:52:40 +0000 From: sven.auhagen@voleatech.de To: axboe@kernel.dk, hdegoede@redhat.com, robh+dt@kernel.org, tglx@linutronix.de, maz@kernel.org, gregory.clement@bootlin.com Cc: linux-ide@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, jason@lakedaemon.net, andrew@lunn.ch, rjw@rjwysocki.net, viresh.kumar@linaro.org, antoine.tenart@bootlin.com, maxime.chevallier@bootlin.com, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com Subject: [PATCH v2 0/9] Armada8k enable per-port SATA interrupts and drop a hack in the IRQ subsystem Date: Wed, 4 Nov 2020 16:52:28 +0100 Message-Id: <20201104155237.77772-1-sven.auhagen@voleatech.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) X-Originating-IP: [109.193.235.168] X-ClientProxiedBy: AM8P190CA0030.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::35) To AM8PR05MB7251.eurprd05.prod.outlook.com (2603:10a6:20b:1d4::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (109.193.235.168) by AM8P190CA0030.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19 via Frontend Transport; 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I talked to Miquèl and I fixed up the last comments from v4. I am looking for feedback if this patch series is now ready to be merged and what should be further changed. Here is the original cover letter: Some time ago, when the initial support for Armada CP110 was contributed, the SATA core was not able to handle per-port interrupts. Despite the hardware reality, the device tree only represents one main interrupt for the two ports. Having both SATA ports enabled at the same time has been achieved by a hack in the ICU driver(1) that faked the use of the two interrupts, no matter which SATA port was in use. Now that the SATA core is ready to handle more than one interrupt, this series adds support for it in the libahci_platform code. The CP110 device tree must be updated to reflect the two SATA ports available and their respective interrupts. To do not break DT backward compatibility, the ahci_platform driver now embeds a special quirk which checks if the DT is valid (only for A8k compatible) and, if needed, creates the two missing sub-nodes, and assign them the relevant "reg" and "interrupts" properties, before removing the main SATA node "interrupts" one. (1) The ICU is an irqchip aggregating the CP110 (south-bridge) interrupts into MSIs for the AP806 (north-bridge). Best Sven Change from v1: * Add a patch to enable custom irq initialization in plattform init host * Add multi_irq_host_ack callback for the msi irq handler * Rework the ahci mvebu patch to initiate the irq and use the new multi_irq_host_ack to handle the custom irq code. Remove the custom irq handler and duplicate code. * Fix the armada8k backwards compatibility code * Rename AHCI_PLATFORM_A8K_QUIRK to AHCI_PLATFORM_ARMADA8K_QUIRK Miquel Raynal (5): ata: ahci: mvebu: Rename a platform data flag ata: ahci: mvebu: Support A8k compatible irqchip/irq-mvebu-icu: Remove the double SATA ports interrupt hack dt-bindings: ata: Update ahci bindings with possible per-port interrupts dt-bindings: ata: Update ahci_mvebu bindings Sven Auhagen (4): ata: ahci: custom irq init for host init ata: ahci: add ack callback to multi irq handler ata: ahci: mvebu: Add support for A8k legacy DT bindings arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts .../devicetree/bindings/ata/ahci-platform.txt | 7 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +- drivers/ata/ahci.h | 2 + drivers/ata/ahci_mvebu.c | 143 ++++++++++++++++-- drivers/ata/libahci.c | 4 + drivers/ata/libahci_platform.c | 19 ++- drivers/irqchip/irq-mvebu-icu.c | 18 --- include/linux/ahci_platform.h | 1 + 8 files changed, 160 insertions(+), 40 deletions(-)