@@ -542,10 +542,11 @@ static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
unsigned int pec_len = i2c->rx_msg->len - 1;
/* Set Receive fifo depth */
- if (rxmsg_len > IIC_RX_FIFO_DEPTH) {
+ if (rxmsg_len + pec_len > IIC_RX_FIFO_DEPTH) {
/*
- * When Rx msg len greater than or equal to Rx fifo capacity
- * Receive fifo depth should set to Rx fifo capacity minus 1
+ * Trailing payload (data + optional PEC) exceeds Rx FIFO
+ * capacity; drain in chunks. Fire RX_FULL when the FIFO is
+ * full and let the ISR re-arm for the remainder.
*/
rfd_set = IIC_RX_FIFO_DEPTH - 1;
i2c->rx_msg->len = rxmsg_len + 1 + pec_len;
@@ -559,11 +560,8 @@ static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
rfd_set = 0;
i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
} else {
- /*
- * When Rx msg len less than Rx fifo capacity
- * Receive fifo depth should set to Rx msg len minus 2
- */
- rfd_set = rxmsg_len - 2;
+ /* Defer RX_FULL until all trailing bytes are in FIFO. */
+ rfd_set = rxmsg_len + pec_len - 1;
i2c->rx_msg->len = rxmsg_len + 1 + pec_len;
}
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
For the normal path of xiic_smbus_block_read_setup() (rxmsg_len less than IIC_RX_FIFO_DEPTH), RFD was programmed to rxmsg_len - 2, which fires the RX_FULL interrupt while the last payload byte is still in flight. xiic_read_rx()'s bytes_rem == 1 branch then sets NACK on that byte still on the wire, truncating the read in the PEC-enabled case. Raise the threshold so RX_FULL fires only once every remaining byte (payload plus optional PEC) is already buffered in the FIFO. That routes the drain through xiic_read_rx()'s bytes_rem == 0 path, which reads everything out and emits the stop cleanly. For the non-PEC path the full payload is still read out through the same bytes_rem == 0 branch; the only user-visible change is that the controller waits one extra byte-time before servicing the interrupt. The deferred-fire formula is rxmsg_len + pec_len - 1, and the RFD register at XIIC_RFD_REG_OFFSET is a 4-bit field. Widen the chunk-vs-defer guard to (rxmsg_len + pec_len > IIC_RX_FIFO_DEPTH) so the boundary case rxmsg_len == IIC_RX_FIFO_DEPTH with PEC enabled cannot write 16 into that 4-bit register; it routes through the chunked drain instead, which already caps RFD at IIC_RX_FIFO_DEPTH - 1. Signed-off-by: Abdurrahman Hussain <abdurrahman@nexthop.ai> --- drivers/i2c/busses/i2c-xiic.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-)