From patchwork Fri Jul 31 12:00:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert ABEL X-Patchwork-Id: 502515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D07221402CD for ; Fri, 31 Jul 2015 22:07:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751234AbbGaMHY (ORCPT ); Fri, 31 Jul 2015 08:07:24 -0400 Received: from smarthost.TechFak.Uni-Bielefeld.DE ([129.70.137.17]:44789 "EHLO smarthost.TechFak.Uni-Bielefeld.DE" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751346AbbGaMHX (ORCPT ); Fri, 31 Jul 2015 08:07:23 -0400 Received: from knoppers.TechFak.Uni-Bielefeld.DE (knoppers.TechFak.Uni-Bielefeld.DE [129.70.129.230]) (Authenticated sender: rabel) by smarthost.TechFak.Uni-Bielefeld.DE (Postfix) with ESMTPA id E462580021; Fri, 31 Jul 2015 14:00:43 +0200 (CEST) From: Robert ABEL To: wsa@the-dreams.de, linux-i2c@vger.kernel.org Cc: michal.simek@xilinx.com, Robert ABEL Subject: [PATCH 2/6] i2x: Xilinx IIC: remove non-initial tabs Date: Fri, 31 Jul 2015 14:00:30 +0200 Message-Id: <1438344034-20211-4-git-send-email-rabel@cit-ec.uni-bielefeld.de> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1438344034-20211-1-git-send-email-rabel@cit-ec.uni-bielefeld.de> References: <1438344034-20211-1-git-send-email-rabel@cit-ec.uni-bielefeld.de> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Signed-off-by: Robert ABEL --- drivers/i2c/busses/i2c-xiic.c | 110 +++++++++++++++++++++--------------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index dd897b5..e566ccb 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -48,28 +48,28 @@ enum xilinx_i2c_state { /** * struct xiic_i2c - Internal representation of the XIIC I2C bus - * @base: Memory base of the HW registers - * @wait: Wait queue for callers - * @adap: Kernel adapter representation - * @tx_msg: Messages from above to be sent - * @lock: Mutual exclusion - * @tx_pos: Current pos in TX message - * @nmsgs: Number of messages in tx_msg - * @state: See STATE_ - * @rx_msg: Current RX message - * @rx_pos: Position within current RX message + * @base: Memory base of the HW registers + * @wait: Wait queue for callers + * @adap: Kernel adapter representation + * @tx_msg: Messages from above to be sent + * @lock: Mutual exclusion + * @tx_pos: Position within current TX message + * @nmsgs: Number of messages in tx_msg + * @state: Current controller state + * @rx_msg: Current RX message + * @rx_pos: Position within current RX message */ struct xiic_i2c { - void __iomem *base; - wait_queue_head_t wait; - struct i2c_adapter adap; - struct i2c_msg *tx_msg; - spinlock_t lock; - unsigned int tx_pos; - unsigned int nmsgs; - enum xilinx_i2c_state state; - struct i2c_msg *rx_msg; - int rx_pos; + void __iomem * base; + wait_queue_head_t wait; + struct i2c_adapter adap; + struct i2c_msg *tx_msg; + spinlock_t lock; + unsigned int tx_pos; + unsigned int nmsgs; + enum xilinx_i2c_state state; + struct i2c_msg *rx_msg; + int rx_pos; }; @@ -78,49 +78,49 @@ struct xiic_i2c { /* * Register offsets in bytes from RegisterBase. */ -#define XIIC_CR_REG (0x00+XIIC_REG_OFFSET) /* Control Register */ -#define XIIC_SR_REG (0x04+XIIC_REG_OFFSET) /* Status Register */ -#define XIIC_DTR_REG (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ -#define XIIC_DRR_REG (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ -#define XIIC_ADR_REG (0x10+XIIC_REG_OFFSET) /* Address Register */ -#define XIIC_TFO_REG (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ -#define XIIC_RFO_REG (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ -#define XIIC_TBA_REG (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ -#define XIIC_RFD_REG (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ -#define XIIC_GPO_REG (0x24+XIIC_REG_OFFSET) /* Output Register */ +#define XIIC_CR_REG (0x00+XIIC_REG_OFFSET) /* Control Register */ +#define XIIC_SR_REG (0x04+XIIC_REG_OFFSET) /* Status Register */ +#define XIIC_DTR_REG (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ +#define XIIC_DRR_REG (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ +#define XIIC_ADR_REG (0x10+XIIC_REG_OFFSET) /* Address Register */ +#define XIIC_TFO_REG (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ +#define XIIC_RFD_REG (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ +#define XIIC_GPO_REG (0x24+XIIC_REG_OFFSET) /* Output Register */ /* Control Register masks */ -#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ -#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ -#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ -#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ -#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ -#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ -#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ /* Status Register masks */ -#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ -#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ -#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ -#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ -#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ -#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ -#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ -#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ +#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ +#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ +#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ +#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ +#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ +#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ +#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ +#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ /* Interrupt Status Register masks Interrupt occurs when... */ -#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ -#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ -#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ -#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ -#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ -#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ -#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ -#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ +#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ +#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ +#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ +#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ +#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ +#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ +#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ +#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ /* The following constants specify the depth of the FIFOs */ -#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ -#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ +#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ +#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ /* The following constants specify groups of interrupts that are typically * enabled or disables at the same time