@@ -917,6 +917,42 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
PCIE1_CLKREQ_N_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
+};
+static const unsigned int qspi0_data_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi1_data_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -1076,6 +1112,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1199,6 +1241,18 @@ static const char * const pcie_groups[] = {
"pcie1_clkreq_n",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -1245,6 +1299,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pcie),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
Add pins, groups, and functions for the Quad SPI Controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - No changes. This depends on "[PATCH 00/60] pinctrl: renesas: Share more pin group data"[1]. Changes compared to the BSP: - Share QSPI pin group data. [1] https://lore.kernel.org/r/cover.1640269757.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779f0.c | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)