diff mbox

pinctrl/amd: Configure GPIO register using BIOS settings

Message ID CY1PR12MB0042F7C1AA27735D3091519BDCF80@CY1PR12MB0042.namprd12.prod.outlook.com
State New
Headers show

Commit Message

Agrawal, Nitesh-kumar Sept. 7, 2016, 8:56 a.m. UTC 
In the function amd_gpio_irq_set_type, use the settings provided by
the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure
the GPIO registers. Ignore the settings from client.

Reviewed-by:Pankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
---
 drivers/pinctrl/pinctrl-amd.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox

Patch

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 828148d..a645082 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -385,12 +385,26 @@  static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	int ret = 0;
 	u32 pin_reg;
 	unsigned long flags;
+        u32 levelTrig;
+        u32 activeLevel;
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
 	spin_lock_irqsave(&gpio_dev->lock, flags);
 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 
+        /*
+         When LevelTrig is set EDGE and activeLevel is set HIGH in BIOS
+         default settings, ignore incoming settings from client and use
+         BIOS settings to configure GPIO register.
+        */
+        levelTrig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF);
+        activeLevel = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
+
+        if((!levelTrig)&&((activeLevel>> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) {
+           type = IRQ_TYPE_EDGE_FALLING;
+        }
+
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_EDGE_RISING:
 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);