| Message ID | 20230901090224.27770-3-krzysztof.kozlowski@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register | expand |
On 1.09.2023 11:02, Krzysztof Kozlowski wrote: > Existing Qualcomm SoCs have the LPASS pin controller slew rate control > in separate register, however this will change with upcoming Qualcomm > SoCs. The slew rate will be part of the main register for pin > configuration, thus second device IO address space is not needed. > > Prepare for supporting new SoCs by adding flag customizing the driver > behavior for slew rate. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ > drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ > 2 files changed, 21 insertions(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > index e2df2193a802..40eb58a3a8cd 100644 > --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > @@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, > const struct lpi_pingroup *g, > unsigned int group, unsigned int slew) > { > + void __iomem *reg; Aaalmost reverse-Christmas-tree! > unsigned long sval; > int slew_offset; > > @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, > if (slew_offset == LPI_NO_SLEW) > return 0; > > + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) > + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; > + else > + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; Perhaps lpi_gpio_read/write could be used here? I guess both ways work though Konrad
On 01/09/2023 14:28, Konrad Dybcio wrote: > On 1.09.2023 11:02, Krzysztof Kozlowski wrote: >> Existing Qualcomm SoCs have the LPASS pin controller slew rate control >> in separate register, however this will change with upcoming Qualcomm >> SoCs. The slew rate will be part of the main register for pin >> configuration, thus second device IO address space is not needed. >> >> Prepare for supporting new SoCs by adding flag customizing the driver >> behavior for slew rate. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ >> 2 files changed, 21 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index e2df2193a802..40eb58a3a8cd 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, >> const struct lpi_pingroup *g, >> unsigned int group, unsigned int slew) >> { >> + void __iomem *reg; > Aaalmost reverse-Christmas-tree! I can fix it. > >> unsigned long sval; >> int slew_offset; >> >> @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, >> if (slew_offset == LPI_NO_SLEW) >> return 0; >> >> + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) >> + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; >> + else >> + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; > Perhaps lpi_gpio_read/write could be used here? > > I guess both ways work though I was thinking about this, but decided not to in favor of duplicating "tlmm_base + offset * group ....". It would not make the code easier to read. Best regards, Krzysztof
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index e2df2193a802..40eb58a3a8cd 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, const struct lpi_pingroup *g, unsigned int group, unsigned int slew) { + void __iomem *reg; unsigned long sval; int slew_offset; @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, if (slew_offset == LPI_NO_SLEW) return 0; + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; + else + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + mutex_lock(&pctrl->lock); - sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval = ioread32(reg); sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); sval |= slew << slew_offset; - iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + iowrite32(sval, reg); mutex_unlock(&pctrl->lock); @@ -452,10 +458,12 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), "TLMM resource not provided\n"); - pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(pctrl->slew_base)) - return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), - "Slew resource not provided\n"); + if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) { + pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->slew_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), + "Slew resource not provided\n"); + } ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index 29047bb80bb8..8a4cd8aef38c 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -60,6 +60,12 @@ struct pinctrl_pin_desc; .nfuncs = 5, \ } +/* + * Slew rate control is done in the same register as rest of the + * pin configuration. + */ +#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) + struct lpi_pingroup { struct group_desc group; unsigned int pin; @@ -82,6 +88,7 @@ struct lpi_pinctrl_variant_data { int ngroups; const struct lpi_function *functions; int nfunctions; + unsigned int flags; }; int lpi_pinctrl_probe(struct platform_device *pdev);
Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ 2 files changed, 21 insertions(+), 6 deletions(-)