| Message ID | 20220929143225.17907-5-hal.feng@linux.starfivetech.com |
|---|---|
| State | New |
| Headers | show |
| Series | Basic StarFive JH7110 RISC-V SoC support | expand |
On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote: > From: Emil Renner Berthing <kernel@esmil.dk> > > This cache controller is also used on the StarFive JH7100 and JH7110 > SoCs. Ditto this patch, hopefully [0] will have landed as 6.1 material before you get around to an actual v2. Thanks, Conor 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/ > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> > --- > Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index ca3b9be58058..ba29ecfd3a92 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -24,6 +24,8 @@ select: > enum: > - sifive,fu540-c000-ccache > - sifive,fu740-c000-ccache > + - starfive,jh7100-ccache > + - starfive,jh7110-ccache > > required: > - compatible > @@ -35,6 +37,8 @@ properties: > - enum: > - sifive,fu540-c000-ccache > - sifive,fu740-c000-ccache > + - starfive,jh7100-ccache > + - starfive,jh7110-ccache > - const: cache > - items: > - const: microchip,mpfs-ccache > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 29/09/2022 16:33, Conor Dooley wrote: > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> This cache controller is also used on the StarFive JH7100 and JH7110 >> SoCs. > > Ditto this patch, hopefully [0] will have landed as 6.1 material > before you get around to an actual v2. > > Thanks, > Conor > > 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/ Also, the l2 cache is being proprely named the ccache (composable cache) as it is not necessarily an L2 cache.
On Mon, 3 Oct 2022 10:26:44 +0100, Ben Dooks wrote: > On 29/09/2022 16:33, Conor Dooley wrote: > > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote: > >> From: Emil Renner Berthing <kernel@esmil.dk> > >> > >> This cache controller is also used on the StarFive JH7100 and JH7110 > >> SoCs. > > > > Ditto this patch, hopefully [0] will have landed as 6.1 material > > before you get around to an actual v2. > > > > Thanks, > > Conor > > > > 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/ > > Also, the l2 cache is being proprely named the ccache (composable cache) > as it is not necessarily an L2 cache. > Thanks for reminding. I will modify the code, based on the patches from Zong Li. I hope his patch series will be merged as soon as possible. Best regards, Hal
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index ca3b9be58058..ba29ecfd3a92 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -24,6 +24,8 @@ select: enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache required: - compatible @@ -35,6 +37,8 @@ properties: - enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache - const: cache - items: - const: microchip,mpfs-ccache