[v1,10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c'

Message ID	20220929143225.17907-11-hal.feng@linux.starfivetech.com
State	New
Headers	show Return-Path: <linux-gpio-owner@vger.kernel.org> From: Hal Feng <hal.feng@linux.starfivetech.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Hal Feng <hal.feng@linux.starfivetech.com>, linux-kernel@vger.kernel.org Subject: [PATCH v1 10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c' Date: Thu, 29 Sep 2022 22:32:05 +0800 Message-Id: <20220929143225.17907-11-hal.feng@linux.starfivetech.com> In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk
Series	Basic StarFive JH7110 RISC-V SoC support \| expand [v1,00/30] Basic StarFive JH7110 RISC-V SoC support [v1,01/30] dt-bindings: riscv: Add StarFive JH7110 bindings [v1,02/30] dt-bindings: timer: Add StarFive JH7110 clint [v1,03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic [v1,04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs [v1,05/30] soc: sifive: l2 cache: Convert to platform driver [v1,06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support [v1,07/30] reset: starfive: jh7100: Use 32bit I/O on 32bit registers [v1,08/30] reset: starfive: jh7100: Use regmap APIs to operate registers [v1,09/30] reset: starfive: jh7100: Move necessary properties to device tree [v1,10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c' [v1,11/30] dt-bindings: reset: Add StarFive JH7110 reset definitions [v1,12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings [v1,13/30] reset: starfive: Add StarFive JH7110 SoC support [v1,14/30] clk: starfive: Factor out common clock driver code [v1,15/30] clk: starfive: Use regmap APIs to operate registers [v1,16/30] dt-bindings: clock: Add StarFive JH7110 system clock definitions [v1,17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings [v1,18/30] clk: starfive: Add StarFive JH7110 system clock driver [v1,19/30] dt-bindings: clock: Add StarFive JH7110 always-on definitions [v1,20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings [v1,21/30] clk: starfive: Add StarFive JH7110 always-on clock driver [v1,22/30] pinctrl: Create subdirectory for StarFive drivers [v1,23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" [v1,24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions [v1,25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings [v1,26/30] pinctrl: starfive: Add StarFive JH7110 driver [v1,27/30] RISC-V: Add initial StarFive JH7110 device tree [v1,28/30] RISC-V: Add StarFive JH7110 VisionFive2 board device tree [v1,29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW [v1,30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options

diff --git a/MAINTAINERS b/MAINTAINERS index f5ca4aefd184..f2319a3b708b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19411,12 +19411,13 @@ F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml F: drivers/pinctrl/pinctrl-starfive.c F: include/dt-bindings/pinctrl/pinctrl-starfive.h -STARFIVE JH7100 RESET CONTROLLER DRIVER +STARFIVE RESET CONTROLLER DRIVER M: Emil Renner Berthing <kernel@esmil.dk> +M: Hal Feng <hal.feng@linux.starfivetech.com> S: Maintained -F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml -F: drivers/reset/reset-starfive-jh7100.c -F: include/dt-bindings/reset/starfive-jh7100.h +F: Documentation/devicetree/bindings/reset/starfive* +F: drivers/reset/reset-starfive.c +F: include/dt-bindings/reset/starfive* STATIC BRANCH/CALL M: Peter Zijlstra <peterz@infradead.org> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 806773e88832..8121de5ecc3c 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -225,12 +225,12 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. -config RESET_STARFIVE_JH7100 - bool "StarFive JH7100 Reset Driver" +config RESET_STARFIVE + bool "StarFive SoC Reset Driver" depends on SOC_STARFIVE || COMPILE_TEST default SOC_STARFIVE help - This enables the reset controller driver for the StarFive JH7100 SoC. + This enables the reset controller driver for the StarFive SoCs. config RESET_SUNPLUS bool "Sunplus SoCs Reset Driver" if COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index cd5cf8e7c6a7..269268a48f56 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o -obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o +obj-$(CONFIG_RESET_STARFIVE) += reset-starfive.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive.c similarity index 70% rename from drivers/reset/reset-starfive-jh7100.c rename to drivers/reset/reset-starfive.c index d3656e99ae0e..56d07bafadd7 100644 --- a/drivers/reset/reset-starfive-jh7100.c +++ b/drivers/reset/reset-starfive.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Reset driver for the StarFive JH7100 SoC + * Reset driver for the StarFive SoC * * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> * Copyright (C) 2021-2022 StarFive Technology Co., Ltd. @@ -36,7 +36,7 @@ static const u32 jh7100_reset_asserted[4] = { 0, }; -struct jh7100_reset { +struct starfive_reset { struct reset_controller_dev rcdev; struct regmap *regmap; u32 assert_offset; @@ -45,16 +45,16 @@ struct jh7100_reset { const u32 *asserted; }; -static inline struct jh7100_reset * -jh7100_reset_from(struct reset_controller_dev *rcdev) +static inline struct starfive_reset * +starfive_reset_from(struct reset_controller_dev *rcdev) { - return container_of(rcdev, struct jh7100_reset, rcdev); + return container_of(rcdev, struct starfive_reset, rcdev); } -static int jh7100_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) +static int starfive_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) { - struct jh7100_reset *data = jh7100_reset_from(rcdev); + struct starfive_reset *data = starfive_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); u32 reg_assert = data->assert_offset + offset * sizeof(u32); @@ -86,34 +86,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev, return ret; } -static int jh7100_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) { - return jh7100_reset_update(rcdev, id, true); + return starfive_reset_update(rcdev, id, true); } -static int jh7100_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) { - return jh7100_reset_update(rcdev, id, false); + return starfive_reset_update(rcdev, id, false); } -static int jh7100_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) { int ret; - ret = jh7100_reset_assert(rcdev, id); + ret = starfive_reset_assert(rcdev, id); if (ret) return ret; - return jh7100_reset_deassert(rcdev, id); + return starfive_reset_deassert(rcdev, id); } -static int jh7100_reset_status(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) { - struct jh7100_reset *data = jh7100_reset_from(rcdev); + struct starfive_reset *data = starfive_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); u32 reg_status = data->status_offset + offset * sizeof(u32); @@ -127,16 +127,16 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, return !((value ^ data->asserted[offset]) & mask); } -static const struct reset_control_ops jh7100_reset_ops = { - .assert = jh7100_reset_assert, - .deassert = jh7100_reset_deassert, - .reset = jh7100_reset_reset, - .status = jh7100_reset_status, +static const struct reset_control_ops starfive_reset_ops = { + .assert = starfive_reset_assert, + .deassert = starfive_reset_deassert, + .reset = starfive_reset_reset, + .status = starfive_reset_status, }; -static int __init jh7100_reset_probe(struct platform_device *pdev) +static int __init starfive_reset_probe(struct platform_device *pdev) { - struct jh7100_reset *data; + struct starfive_reset *data; int ret; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); @@ -171,7 +171,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) return ret; } - data->rcdev.ops = &jh7100_reset_ops; + data->rcdev.ops = &starfive_reset_ops; data->rcdev.owner = THIS_MODULE; data->rcdev.nr_resets = data->nr_resets; data->rcdev.dev = &pdev->dev; @@ -182,16 +182,16 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) return devm_reset_controller_register(&pdev->dev, &data->rcdev); } -static const struct of_device_id jh7100_reset_dt_ids[] = { +static const struct of_device_id starfive_reset_dt_ids[] = { { .compatible = "starfive,jh7100-reset" }, { /* sentinel */ } }; -static struct platform_driver jh7100_reset_driver = { +static struct platform_driver starfive_reset_driver = { .driver = { - .name = "jh7100-reset", - .of_match_table = jh7100_reset_dt_ids, + .name = "starfive-reset", + .of_match_table = starfive_reset_dt_ids, .suppress_bind_attrs = true, }, }; -builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe); +builtin_platform_driver_probe(starfive_reset_driver, starfive_reset_probe);

[v1,10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c'

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Patch