| Message ID | 20220613031854.1571357-1-ping.bai@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: imx: Add the zero base flag for imx93 | expand |
Ping... BR > Subject: [PATCH] pinctrl: imx: Add the zero base flag for imx93 > > On i.MX93, the pin mux reg offset is from 0x0, so need to add the > 'ZERO_OFFSET_VALID' flag to make sure the pin at mux offset 0 can be found. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > drivers/pinctrl/freescale/pinctrl-imx93.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c > b/drivers/pinctrl/freescale/pinctrl-imx93.c > index c0630f69e995..417e41b37a6f 100644 > --- a/drivers/pinctrl/freescale/pinctrl-imx93.c > +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c > @@ -239,6 +239,7 @@ static const struct pinctrl_pin_desc > imx93_pinctrl_pads[] = { static const struct imx_pinctrl_soc_info > imx93_pinctrl_info = { > .pins = imx93_pinctrl_pads, > .npins = ARRAY_SIZE(imx93_pinctrl_pads), > + .flags = ZERO_OFFSET_VALID, > .gpr_compatible = "fsl,imx93-iomuxc-gpr", }; > > -- > 2.25.1
On Mon, Jun 13, 2022 at 5:17 AM Jacky Bai <ping.bai@nxp.com> wrote: > On i.MX93, the pin mux reg offset is from 0x0, > so need to add the 'ZERO_OFFSET_VALID' flag to make > sure the pin at mux offset 0 can be found. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> No reply from maintainers for an urgent fix for two weeks -> patch applied. Jacky, maybe you should be listed as comaintainer for the freescale pin controller if you are doing active maintenance on it? Yours, Linus Walleij
> Subject: Re: [PATCH] pinctrl: imx: Add the zero base flag for imx93 > > On Mon, Jun 13, 2022 at 5:17 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > On i.MX93, the pin mux reg offset is from 0x0, so need to add the > > 'ZERO_OFFSET_VALID' flag to make sure the pin at mux offset 0 can be > > found. > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > No reply from maintainers for an urgent fix for two weeks -> patch applied. > > Jacky, maybe you should be listed as comaintainer for the freescale pin > controller if you are doing active maintenance on it? > Yes, I can help on this. BR > Yours, > Linus Walleij
On Mon, Jul 4, 2022 at 8:04 AM Jacky Bai <ping.bai@nxp.com> wrote: > > Subject: Re: [PATCH] pinctrl: imx: Add the zero base flag for imx93 > > On Mon, Jun 13, 2022 at 5:17 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > > > On i.MX93, the pin mux reg offset is from 0x0, so need to add the > > > 'ZERO_OFFSET_VALID' flag to make sure the pin at mux offset 0 can be > > > found. > > > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > > > No reply from maintainers for an urgent fix for two weeks -> patch applied. > > > > Jacky, maybe you should be listed as comaintainer for the freescale pin > > controller if you are doing active maintenance on it? > > Yes, I can help on this. Please send a patch to MAINATINERS adding yourself as maintainer and CC the other maintainers listed there. Maybe you have some internal NXP mail list and procedure to follow too, no idea :D discuss amongs yourselves if necessary, but I really like active maintainers. Thanks! Linus Walleij
diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c index c0630f69e995..417e41b37a6f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx93.c +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -239,6 +239,7 @@ static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = { static const struct imx_pinctrl_soc_info imx93_pinctrl_info = { .pins = imx93_pinctrl_pads, .npins = ARRAY_SIZE(imx93_pinctrl_pads), + .flags = ZERO_OFFSET_VALID, .gpr_compatible = "fsl,imx93-iomuxc-gpr", };
On i.MX93, the pin mux reg offset is from 0x0, so need to add the 'ZERO_OFFSET_VALID' flag to make sure the pin at mux offset 0 can be found. Signed-off-by: Jacky Bai <ping.bai@nxp.com> --- drivers/pinctrl/freescale/pinctrl-imx93.c | 1 + 1 file changed, 1 insertion(+)