| Message ID | 20211110225808.16388-6-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Renesas RZ/G2L IRQC support | expand |
On Thu, Nov 11, 2021 at 12:59 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Number of GPIO IRQ's supported by the chip is not always supported GPIO IRQs by the chip > equal to the number of GPIO pins. For example on Renesas RZ/G2L > SoC where it has GPIO0-122 pins but at a give point a maximum > of only 32 GPIO pins can be used as IRQ lines in the IRQC domain. > > This patch adds ngirq member to struct gpio_irq_chip and passes > this as a size to irq_domain_create_hierarchy()/irq_domain_create_simple() > if it is being set in the driver otherwise fallbacks to using ngpio. ... > gc->irq.domain = irq_domain_create_hierarchy( > gc->irq.parent_domain, > 0, > - gc->ngpio, > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, You may use ?: instead as it's done somewhere else in this module. > gc->irq.fwnode, > &gc->irq.child_irq_domain_ops, > gc); ... > gc->irq.domain = irq_domain_create_simple(fwnode, > - gc->ngpio, > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, Ditto. > gc->irq.first, > gc->irq.domain_ops ?: &gpiochip_domain_ops, (^^^ You see?) > gc); ... > + /** > + * @ngirq: > + * > + * The number of GPIO IRQ's handled by this IRQ domain; usually is handled GPIO IRQs > + * equal to ngpio Missed period. > + */
Hi Andy, Thank you for the review. On Thu, Nov 11, 2021 at 8:52 PM Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > On Thu, Nov 11, 2021 at 12:59 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Number of GPIO IRQ's supported by the chip is not always > > supported GPIO IRQs by the chip > will update the change log. > > equal to the number of GPIO pins. For example on Renesas RZ/G2L > > SoC where it has GPIO0-122 pins but at a give point a maximum > > of only 32 GPIO pins can be used as IRQ lines in the IRQC domain. > > > > This patch adds ngirq member to struct gpio_irq_chip and passes > > this as a size to irq_domain_create_hierarchy()/irq_domain_create_simple() > > if it is being set in the driver otherwise fallbacks to using ngpio. > > ... > > > gc->irq.domain = irq_domain_create_hierarchy( > > gc->irq.parent_domain, > > 0, > > - gc->ngpio, > > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, > > You may use ?: instead as it's done somewhere else in this module. > Agreed will do. > > gc->irq.fwnode, > > &gc->irq.child_irq_domain_ops, > > gc); > > ... > > > gc->irq.domain = irq_domain_create_simple(fwnode, > > - gc->ngpio, > > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, > > Ditto. > > > gc->irq.first, > > gc->irq.domain_ops ?: &gpiochip_domain_ops, > > (^^^ You see?) > Thanks for the pointer. > > gc); > > ... > > > + /** > > + * @ngirq: > > + * > > + * The number of GPIO IRQ's handled by this IRQ domain; usually is > > handled GPIO IRQs > OK, will update the description as mentioned above. > > + * equal to ngpio > > Missed period. > Ouch. Cheers, Prabhakar > > + */ > > -- > With Best Regards, > Andy Shevchenko
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 30aabef37468..36a8eefe91b9 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1185,7 +1185,7 @@ static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc) gc->irq.domain = irq_domain_create_hierarchy( gc->irq.parent_domain, 0, - gc->ngpio, + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, gc->irq.fwnode, &gc->irq.child_irq_domain_ops, gc); @@ -1528,7 +1528,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gc, } else { /* Some drivers provide custom irqdomain ops */ gc->irq.domain = irq_domain_create_simple(fwnode, - gc->ngpio, + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, gc->irq.first, gc->irq.domain_ops ?: &gpiochip_domain_ops, gc); diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index a0f9901dcae6..129945bfe3e7 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -51,6 +51,14 @@ struct gpio_irq_chip { */ const struct irq_domain_ops *domain_ops; + /** + * @ngirq: + * + * The number of GPIO IRQ's handled by this IRQ domain; usually is + * equal to ngpio + */ + u16 ngirq; + #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY /** * @fwnode:
Number of GPIO IRQ's supported by the chip is not always equal to the number of GPIO pins. For example on Renesas RZ/G2L SoC where it has GPIO0-122 pins but at a give point a maximum of only 32 GPIO pins can be used as IRQ lines in the IRQC domain. This patch adds ngirq member to struct gpio_irq_chip and passes this as a size to irq_domain_create_hierarchy()/irq_domain_create_simple() if it is being set in the driver otherwise fallbacks to using ngpio. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/gpio/gpiolib.c | 4 ++-- include/linux/gpio/driver.h | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-)