| Message ID | 20211110224622.16022-4-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | RZ/G2L: pinctrl: Support to get/set drive-strength and output-impedance-ohms | expand |
Hi Prabhakar, On Wed, Nov 10, 2021 at 11:46 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add helper functions to read/read modify write pin config. > > Switch to use helper functions for pins supporting PIN_CONFIG_INPUT_ENABLE > capabilities. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2->v3 > * Dropped duplicate masking in rzg2l_read_pin_config > * Dropped port_pin flag > * Dropped spinlocks around read/write You do need the spinlock in the read-modify-write case. No worries, I'll add it back while applying. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.17. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Fri, Nov 12, 2021 at 2:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Nov 10, 2021 at 11:46 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add helper functions to read/read modify write pin config. > > > > Switch to use helper functions for pins supporting PIN_CONFIG_INPUT_ENABLE > > capabilities. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v2->v3 > > * Dropped duplicate masking in rzg2l_read_pin_config > > * Dropped port_pin flag > > * Dropped spinlocks around read/write > > You do need the spinlock in the read-modify-write case. > Ouch I mistook your comment of dropping the lock entirely! > No worries, I'll add it back while applying. > Thank you. Cheers, Prabhakar > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-pinctrl-for-v5.17. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index be9af717a497..984c19328efa 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -424,6 +424,36 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, return ret; } +static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, + u8 bit, u32 mask) +{ + void __iomem *addr = pctrl->base + offset; + + /* handle _L/_H for 32-bit register read/write */ + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + return (readl(addr) >> (bit * 8)) & mask; +} + +static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, + u8 bit, u32 mask, u32 val) +{ + void __iomem *addr = pctrl->base + offset; + u32 reg; + + /* handle _L/_H for 32-bit register read/write */ + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + reg = readl(addr) & ~(mask << (bit * 8)); + writel(reg | (val << (bit * 8)), addr); +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -432,8 +462,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; - u32 port_offset = 0, reg; unsigned int arg = 0; + u32 port_offset = 0; unsigned long flags; void __iomem *addr; u32 cfg = 0; @@ -452,17 +482,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - spin_lock_irqsave(&pctrl->lock, flags); - /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port_offset); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - reg = readl(addr) & (IEN_MASK << (bit * 8)); - arg = (reg >> (bit * 8)) & 0x1; - spin_unlock_irqrestore(&pctrl->lock, flags); + arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); break; case PIN_CONFIG_POWER_SOURCE: { @@ -502,7 +522,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - u32 port_offset = 0, reg; + u32 port_offset = 0; unsigned long flags; void __iomem *addr; unsigned int i; @@ -528,17 +548,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port_offset); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - spin_lock_irqsave(&pctrl->lock, flags); - reg = readl(addr) & ~(IEN_MASK << (bit * 8)); - writel(reg | (arg << (bit * 8)), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); + rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); break; }