| Message ID | 20210524092605.734-2-lakshmi.sowjanya.d@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add pinctrl support for Intel Keem Bay SoC | expand |
On Mon, May 24, 2021 at 11:26 AM <lakshmi.sowjanya.d@intel.com> wrote: > From: "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@intel.com> > > Add Device Tree bindings documentation for Intel Keem Bay > SoC's pin controller. > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file > > Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > Signed-off-by: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com> > Acked-by: Mark Gross <mgross@linux.intel.com> So since this thing has device tree bindings I suppose it is one of those intel-but-not-x86-and-not-acpi things that Andy should not merge through his tree? I bet he wants to take a look though, so keep Andy posted. Yours, Linus Walleij
On Thu, May 27, 2021 at 01:19:36AM +0200, Linus Walleij wrote: > On Mon, May 24, 2021 at 11:26 AM <lakshmi.sowjanya.d@intel.com> wrote: > > > From: "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@intel.com> > > > > Add Device Tree bindings documentation for Intel Keem Bay > > SoC's pin controller. > > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file > > > > Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > > Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > > Signed-off-by: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com> > > Acked-by: Mark Gross <mgross@linux.intel.com> > > So since this thing has device tree bindings I suppose it is one > of those intel-but-not-x86-and-not-acpi things that Andy should > not merge through his tree? > > I bet he wants to take a look though, so keep Andy posted. Yeah, this is the series I have reviewed couple of times internally, but then it lost on cracks and somebody decided to submit (forgetting to include me) to the mailing list. In any case some points about this: - this is ARM based platform - this pin control doesn't have anything in common with x86 LPSS pin control - Lighting Mountain is a former MIPS-based SoC with x86 core I.o.w. they all are different. I doubt the unification with equilibrium may have happened. But I think it's fine to continue the review publicly. We will see the potential issues, maintainer's desires, etc earlier. Btw, thanks for your preliminary review!
Hi Lakshmi, some more review of the bindings! On Mon, May 24, 2021 at 11:26 AM <lakshmi.sowjanya.d@intel.com> wrote: > +properties: > + compatible: > + const: intel,keembay-pinctrl > + > + reg: > + maxItems: 2 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 The code uses "num-gpios" but should be using "ngpios" which is the standard. > + interrupts: > + description: > + Specifies the interrupt lines to be used by the controller. > + maxItems: 8 We need to figure out how these interrupt assign to GPIOs, and it is relevant to write that already here, om the description. It is fine if the same info is duplicated in the driver. > +patternProperties: > + '^.$': > + type: object Certainly these nodes can have a strict name? Use includes for checking standard attributes: $ref: pinmux-node.yaml# $ref: pincfg-node.yaml# > + description: > + Child nodes can be specified to contain pin configuration information, > + which can then be utilized by pinctrl client devices. > + The following properties are supported. > + > + properties: > + pins: > + description: | > + The name(s) of the pins to be configured in the child node. > + Supported pin names are "GPIO0" up to "GPIO79". (...) > + bias-disable: > + type: boolean Using $ref: pincfg-node.yaml# this becomes bias-disable: true etc. > + drive-strength: > + enum: [2, 4, 8, 12] This needs to be specified though. > + slew-rate: > + description: | > + 0: Fast > + 1: Slow > + enum: [0, 1] And this. Yours, Linus Walleij
Hi Linus Walleij Thanks for the review. Regards, Lakshmi -----Original Message----- From: Linus Walleij <linus.walleij@linaro.org> Sent: Thursday, May 27, 2021 4:12 PM To: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com> Cc: open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; linux-kernel <linux-kernel@vger.kernel.org>; Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; Saha, Tamal <tamal.saha@intel.com> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver Hi Lakshmi, some more review of the bindings! On Mon, May 24, 2021 at 11:26 AM <lakshmi.sowjanya.d@intel.com> wrote: > +properties: > + compatible: > + const: intel,keembay-pinctrl > + > + reg: > + maxItems: 2 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 The code uses "num-gpios" but should be using "ngpios" which is the standard. -- Will update in the next version > + interrupts: > + description: > + Specifies the interrupt lines to be used by the controller. > + maxItems: 8 We need to figure out how these interrupt assign to GPIOs, and it is relevant to write that already here, om the description. It is fine if the same info is duplicated in the driver. -- Shall document it properly in next version > +patternProperties: > + '^.$': > + type: object Certainly these nodes can have a strict name? --I will change the name accordingly. Use includes for checking standard attributes: $ref: pinmux-node.yaml# $ref: pincfg-node.yaml# --I will use the suggested includes. > + description: > + Child nodes can be specified to contain pin configuration information, > + which can then be utilized by pinctrl client devices. > + The following properties are supported. > + > + properties: > + pins: > + description: | > + The name(s) of the pins to be configured in the child node. > + Supported pin names are "GPIO0" up to "GPIO79". (...) > + bias-disable: > + type: boolean Using $ref: pincfg-node.yaml# this becomes bias-disable: true etc. --Thanks! Will update in next version. > + drive-strength: > + enum: [2, 4, 8, 12] This needs to be specified though. > + slew-rate: > + description: | > + 0: Fast > + 1: Slow > + enum: [0, 1] And this. --Will specify the enums in next version. Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml new file mode 100644 index 000000000000..8d45eddf972f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay pin controller Device Tree Bindings + +maintainers: + - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> + +description: | + Intel Keem Bay SoC integrates a pin controller which enables control + of pin directions, input/output values and configuration + for a total of 80 pins. + +properties: + compatible: + const: intel,keembay-pinctrl + + reg: + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupts: + description: + Specifies the interrupt lines to be used by the controller. + maxItems: 8 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '^.$': + type: object + + description: + Child nodes can be specified to contain pin configuration information, + which can then be utilized by pinctrl client devices. + The following properties are supported. + + properties: + pins: + description: | + The name(s) of the pins to be configured in the child node. + Supported pin names are "GPIO0" up to "GPIO79". + + bias-disable: + type: boolean + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [2, 4, 8, 12] + + bias-bus-hold: + type: boolean + + input-schmitt-enable: + type: boolean + + slew-rate: + description: | + 0: Fast + 1: Slow + enum: [0, 1] + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + // Example 1 + pinctrl@600B0000 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600b0000 0x88>, + <0x600b0190 0x1ac>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // Example 2 + pinctrl@600C0000 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600c0000 0x88>, + <0x600c0190 0x1ac>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + spi_pinconf { + pins = "GPIO10", "GPIO11"; + drive-strength = <4>; + bias-pull-down; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 81e1edeceae4..1991899c12e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14445,6 +14445,11 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git F: drivers/pinctrl/intel/ +PIN CONTROLLER - KEEMBAY +M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> +S: Supported +F: drivers/pinctrl/pinctrl-keembay* + PIN CONTROLLER - MEDIATEK M: Sean Wang <sean.wang@kernel.org> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)