| Message ID | 20200601073604.26289-1-saraon640529@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | gpio:asm28xx-18xx: new driver | expand |
Hi Richard,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on gpio/for-next]
[also build test WARNING on v5.7 next-20200529]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Richard-Hsu/gpio-asm28xx-18xx-new-driver/20200601-160444
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce (this is a W=1 build):
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/gpio/gpio-asm28xx-18xx.c:69:6: warning: no previous prototype for 'pci_config_pm_runtime_get' [-Wmissing-prototypes]
69 | void pci_config_pm_runtime_get(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpio/gpio-asm28xx-18xx.c:91:6: warning: no previous prototype for 'pci_config_pm_runtime_put' [-Wmissing-prototypes]
91 | void pci_config_pm_runtime_put(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
vim +/pci_config_pm_runtime_get +69 drivers/gpio/gpio-asm28xx-18xx.c
68
> 69 void pci_config_pm_runtime_get(struct pci_dev *pdev)
70 {
71 struct device *dev = &pdev->dev;
72 struct device *parent = dev->parent;
73
74 if (parent)
75 pm_runtime_get_sync(parent);
76 pm_runtime_get_noresume(dev);
77 /*
78 * pdev->current_state is set to PCI_D3cold during suspending,
79 * so wait until suspending completes
80 */
81 pm_runtime_barrier(dev);
82 /*
83 * Only need to resume devices in D3cold, because config
84 * registers are still accessible for devices suspended but
85 * not in D3cold.
86 */
87 if (pdev->current_state == PCI_D3cold)
88 pm_runtime_resume(dev);
89 }
90
> 91 void pci_config_pm_runtime_put(struct pci_dev *pdev)
92 {
93 struct device *dev = &pdev->dev;
94 struct device *parent = dev->parent;
95
96 pm_runtime_put(dev);
97 if (parent)
98 pm_runtime_put_sync(parent);
99 }
100
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[+cc Lee in case he can shed light on the MFD question below] On Mon, Jun 01, 2020 at 03:36:04PM +0800, Richard Hsu wrote: > Hi Bjorn Helgaas, > 1. What are the other functions and where is the other driver? > >PCI bus and GPIO can be considered as two functions independently. > And the driver is located at drivers/gpio/gpio-amd8111.c I'm obviously missing the point here; sorry for being slow. drivers/gpio/gpio-amd8111.c uses for_each_pci_dev() to look for PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS [1022:746b] devices. drivers/i2c/busses/i2c-amd756.c claims that same device using the normal PCI probe mechanism. In this case both i2c-amd756 and gpio-amd8111 want to use the same device, so there's at least a reason why gpio-amd8111 uses the non-standard mechanism. Your driver looks for PCI_VENDOR_ID_ASMEDIA devices: [1b21:2824], [1b21:2812], [1b21:2806], [1b21:1824], etc). But I haven't found a second driver that needs to claim these devices. I can't tell what any of these devices are (other than that they seem to have some GPIO). You might want to add them to the Linux PCI database at https://pci-ids.ucw.cz/read/PC/1b21 . If you do, then "lspci" will show the correct names for them. You mention below that these devices are PCIe bridges. If that's the case, they would be claimed by the "pcieport" driver in the PCI core (drivers/pci/pcie/portdrv_pci.c). If you collect the output of "sudo lspci -vvxxxx", it would tell us whether the pcieport driver will claim it. If it does, then we have a problem because the PCIe port services (AER, PME, DPC, etc) currently require pcieport. If you want the AER, PME, etc functionality in addition to GPIO, then we have to figure out how to coordinate things. > 2.We end up with multiple drivers controlling the device without > any coordination between them? > >Yes,because two functions are independently in the device,and > the main driver for PCI bus function is more important.We wish > they can't be affected and coordinated between two drivers > as much as possible.If main driver is affected,it is more > serious. > In our case,we have gpio registers on pci configuration space > of asm28xx pci-e bridge(with main pci bus driver).If we want > to use it by another driver that use gpio subsystem /sys/class/ > gpio/(sysfs interface).I find the driver(gpio-amd8111.c) that > meet our request.Sorry! i am not best friend with git,and > reply mail in the same way. > > > Hi Bartosz Golaszewski, > Thank you.And i have studied PCI MFD device in drivers/mfd. I'm not familiar with drivers/mfd. It looks like it might be useful for cases where a single PCI function implements multiple sorts of functionality. But if the problem is that you have a single function that is a PCIe switch port and also implements some GPIOs, I doubt drivers/mfd will help. In that case, both the existing pcieport driver and your new gpio-asm28xx-18xx driver would need to operate the same function, and we'd have to make some significant changes to both of them to fit into the MFD framework. Long-term, I think it would be good to move the pcieport things directly into the PCI core instead of being a separate driver. We've tripped over this problem before with things like performance counters in PCIe ports. > Maybe,it is not what i am looking for.This type of device > include core and miscellaneous function drivers.And function > drivers export resources(io/mem/dma) to sysfs.Fist,we can't > implement another pci bus driver as core driver,and secondly, > it don't use gpio subsystem with /sys/class/gpio/(sysfs > interface). > So,you will review this driver and upstream to mainline > kernel?
Hi Bjorn Helgaas,
Thank for your detailed explanation and benefited me a lot.
I am sorry for your confusion. As you mentioned, i have a single PCIe switch port
and also implements some GPIOs.
>Your driver looks for PCI_VENDOR_ID_ASMEDIA devices: [1b21:2824], [1b21:2812], [1b21:2806], [1b21:1824], etc).
>But I haven't found a second driver that needs to claim these devices.
these devices are PCIe switch port and use "pcieport" as main driver.
Hi Bartosz Golaszewski and linus Walleij,
Thanks for your help. I almost know the problem of this driver. Sorry! This is my mistake to use driver's framework incorrectly.
BR,
Richard
-----Original Message-----
From: Bjorn Helgaas <helgaas@kernel.org>
Sent: Saturday, June 6, 2020 1:13 AM
To: Richard Hsu <saraon640529@gmail.com>
Cc: Richard Hsu(許育彰) <Richard_Hsu@asmedia.com.tw>; Yd Tseng(曾裕達) <Yd_Tseng@asmedia.com.tw>; Jesse1 Chang(張國器) <Jesse1_Chang@asmedia.com.tw>; linus.walleij@linaro.org; bgolaszewski@baylibre.com; bhelgaas@google.com; linux-gpio@vger.kernel.org; linux-pci@vger.kernel.org; Lee Jones <lee.jones@linaro.org>
Subject: Re: [PATCH] gpio:asm28xx-18xx: new driver
[+cc Lee in case he can shed light on the MFD question below]
On Mon, Jun 01, 2020 at 03:36:04PM +0800, Richard Hsu wrote:
> Hi Bjorn Helgaas,
> 1. What are the other functions and where is the other driver?
> >PCI bus and GPIO can be considered as two functions independently.
> And the driver is located at drivers/gpio/gpio-amd8111.c
I'm obviously missing the point here; sorry for being slow.
drivers/gpio/gpio-amd8111.c uses for_each_pci_dev() to look for PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS [1022:746b] devices.
drivers/i2c/busses/i2c-amd756.c claims that same device using the normal PCI probe mechanism.
In this case both i2c-amd756 and gpio-amd8111 want to use the same device, so there's at least a reason why gpio-amd8111 uses the non-standard mechanism.
Your driver looks for PCI_VENDOR_ID_ASMEDIA devices: [1b21:2824], [1b21:2812], [1b21:2806], [1b21:1824], etc). But I haven't found a second driver that needs to claim these devices.
I can't tell what any of these devices are (other than that they seem to have some GPIO). You might want to add them to the Linux PCI database at https://pci-ids.ucw.cz/read/PC/1b21 . If you do, then "lspci" will show the correct names for them.
You mention below that these devices are PCIe bridges. If that's the case, they would be claimed by the "pcieport" driver in the PCI core (drivers/pci/pcie/portdrv_pci.c). If you collect the output of "sudo lspci -vvxxxx", it would tell us whether the pcieport driver will claim it.
If it does, then we have a problem because the PCIe port services (AER, PME, DPC, etc) currently require pcieport. If you want the AER, PME, etc functionality in addition to GPIO, then we have to figure out how to coordinate things.
> 2.We end up with multiple drivers controlling the device without any
> coordination between them?
> >Yes,because two functions are independently in the device,and the
> main driver for PCI bus function is more important.We wish they can't
> be affected and coordinated between two drivers as much as possible.If
> main driver is affected,it is more serious.
> In our case,we have gpio registers on pci configuration space of
> asm28xx pci-e bridge(with main pci bus driver).If we want to use it by
> another driver that use gpio subsystem /sys/class/ gpio/(sysfs
> interface).I find the driver(gpio-amd8111.c) that meet our
> request.Sorry! i am not best friend with git,and reply mail in the
> same way.
>
>
> Hi Bartosz Golaszewski,
> Thank you.And i have studied PCI MFD device in drivers/mfd.
I'm not familiar with drivers/mfd. It looks like it might be useful for cases where a single PCI function implements multiple sorts of functionality.
But if the problem is that you have a single function that is a PCIe switch port and also implements some GPIOs, I doubt drivers/mfd will help. In that case, both the existing pcieport driver and your new gpio-asm28xx-18xx driver would need to operate the same function, and we'd have to make some significant changes to both of them to fit into the MFD framework.
Long-term, I think it would be good to move the pcieport things directly into the PCI core instead of being a separate driver. We've tripped over this problem before with things like performance counters in PCIe ports.
> Maybe,it is not what i am looking for.This type of device include core
> and miscellaneous function drivers.And function drivers export
> resources(io/mem/dma) to sysfs.Fist,we can't implement another pci bus
> driver as core driver,and secondly, it don't use gpio subsystem with
> /sys/class/gpio/(sysfs interface).
> So,you will review this driver and upstream to mainline kernel?
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diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1b96169d84f7..932f128f18c9 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -113,6 +113,13 @@ config GPIO_AMDPT driver for GPIO functionality on Promontory IOHub Require ACPI ASL code to enumerate as a platform device. +config GPIO_ASM28XX + tristate "Asmedia 28XX/18XX GPIO support" + depends on PCI + select GPIO_GENERIC + help + Driver for GPIO functionality on Asmedia 28XX and 18XX PCI-E Bridge. + config GPIO_ASPEED tristate "Aspeed GPIO support" depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b2cfc21a97f3..0cee016f9d2f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o +obj-$(CONFIG_GPIO_ASM28XX) += gpio-asm28xx-18xx.o obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o diff --git a/drivers/gpio/gpio-asm28xx-18xx.c b/drivers/gpio/gpio-asm28xx-18xx.c new file mode 100644 index 000000000000..8c1972044c80 --- /dev/null +++ b/drivers/gpio/gpio-asm28xx-18xx.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Asmedia 28xx/18xx GPIO driver + * + * Copyright (C) 2020 ASMedia Technology Inc. + * Author: Richard Hsu <Richard_Hsu@asmedia.com.tw> + */ + + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/gpio/driver.h> +#include <linux/pci.h> +#include <linux/spinlock.h> +#include <linux/pm_runtime.h> +#include <linux/bits.h> + + +/* GPIO registers offsets */ +#define ASM_GPIO_CTRL 0x920 +#define ASM_GPIO_OUTPUT 0x928 +#define ASM_GPIO_INPUT 0x930 +#define ASM_REG_SWITCH 0xFFF + +#define ASM_REG_SWITCH_CTL 0x01 + +#define ASM_GPIO_PIN5 5 +#define ASM_GPIO_DEFAULT 0 + + +#define PCI_DEVICE_ID_ASM_28XX_PID1 0x2824 +#define PCI_DEVICE_ID_ASM_28XX_PID2 0x2812 +#define PCI_DEVICE_ID_ASM_28XX_PID3 0x2806 +#define PCI_DEVICE_ID_ASM_18XX_PID1 0x1824 +#define PCI_DEVICE_ID_ASM_18XX_PID2 0x1812 +#define PCI_DEVICE_ID_ASM_18XX_PID3 0x1806 +#define PCI_DEVICE_ID_ASM_81XX_PID1 0x812a +#define PCI_DEVICE_ID_ASM_81XX_PID2 0x812b +#define PCI_DEVICE_ID_ASM_80XX_PID1 0x8061 + +/* + * Data for PCI driver interface + * + * This data only exists for exporting the supported + * PCI ids via MODULE_DEVICE_TABLE. We do not actually + * register a pci_driver, because someone else might one day + * want to register another driver on the same PCI id. + */ +static const struct pci_device_id pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_28XX_PID1), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_28XX_PID2), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_28XX_PID3), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_18XX_PID1), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_18XX_PID2), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_18XX_PID3), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_81XX_PID1), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_81XX_PID2), 0 }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, PCI_DEVICE_ID_ASM_80XX_PID1), 0 }, + { 0, }, /* terminate list */ +}; +MODULE_DEVICE_TABLE(pci, pci_tbl); + +struct asm28xx_gpio { + struct gpio_chip chip; + struct pci_dev *pdev; + spinlock_t lock; +}; + +void pci_config_pm_runtime_get(struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + + if (parent) + pm_runtime_get_sync(parent); + pm_runtime_get_noresume(dev); + /* + * pdev->current_state is set to PCI_D3cold during suspending, + * so wait until suspending completes + */ + pm_runtime_barrier(dev); + /* + * Only need to resume devices in D3cold, because config + * registers are still accessible for devices suspended but + * not in D3cold. + */ + if (pdev->current_state == PCI_D3cold) + pm_runtime_resume(dev); +} + +void pci_config_pm_runtime_put(struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + + pm_runtime_put(dev); + if (parent) + pm_runtime_put_sync(parent); +} + +static int asm28xx_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + if (offset == ASM_GPIO_PIN5) + return -ENODEV; + + return 0; +} + +static void asm28xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct asm28xx_gpio *agp = gpiochip_get_data(chip); + u8 temp; + unsigned long flags; + + pci_config_pm_runtime_get(agp->pdev); + spin_lock_irqsave(&agp->lock, flags); + pci_read_config_byte(agp->pdev, ASM_GPIO_OUTPUT, &temp); + if (value) + temp |= BIT(offset); + else + temp &= ~BIT(offset); + + pci_write_config_byte(agp->pdev, ASM_GPIO_OUTPUT, temp); + spin_unlock_irqrestore(&agp->lock, flags); + pci_config_pm_runtime_put(agp->pdev); + dev_dbg(chip->parent, "ASMEDIA-28xx/18xx gpio %d set %d reg=%02x\n", offset, value, temp); +} + +static int asm28xx_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct asm28xx_gpio *agp = gpiochip_get_data(chip); + u8 temp; + unsigned long flags; + + pci_config_pm_runtime_get(agp->pdev); + spin_lock_irqsave(&agp->lock, flags); + pci_read_config_byte(agp->pdev, ASM_GPIO_INPUT, &temp); + spin_unlock_irqrestore(&agp->lock, flags); + pci_config_pm_runtime_put(agp->pdev); + + dev_dbg(chip->parent, "ASMEDIA-28xx/18xx GPIO Pin %d get reg=%02x\n", offset, temp); + return (temp & BIT(offset)) ? 1 : 0; +} + +static int asm28xx_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value) +{ + struct asm28xx_gpio *agp = gpiochip_get_data(chip); + u8 temp; + unsigned long flags; + + pci_config_pm_runtime_get(agp->pdev); + spin_lock_irqsave(&agp->lock, flags); + pci_read_config_byte(agp->pdev, ASM_GPIO_CTRL, &temp); + temp |= BIT(offset); + pci_write_config_byte(agp->pdev, ASM_GPIO_CTRL, temp); + spin_unlock_irqrestore(&agp->lock, flags); + pci_config_pm_runtime_put(agp->pdev); + dev_dbg(chip->parent, "ASMEDIA-28xx/18xx dirout gpio %d reg=%02x\n", offset, temp); + + return 0; +} + +static int asm28xx_gpio_dirin(struct gpio_chip *chip, unsigned offset) +{ + struct asm28xx_gpio *agp = gpiochip_get_data(chip); + u8 temp; + unsigned long flags; + + pci_config_pm_runtime_get(agp->pdev); + spin_lock_irqsave(&agp->lock, flags); + pci_read_config_byte(agp->pdev, ASM_GPIO_CTRL, &temp); + temp &= ~BIT(offset); + pci_write_config_byte(agp->pdev, ASM_GPIO_CTRL, temp); + spin_unlock_irqrestore(&agp->lock, flags); + pci_config_pm_runtime_put(agp->pdev); + dev_dbg(chip->parent, "ASMEDIA-28xx/18xx dirin gpio %d reg=%02x\n", offset, temp); + + return 0; +} + +static struct asm28xx_gpio gp = { + .chip = { + .label = "ASM28XX-18XX GPIO", + .owner = THIS_MODULE, + .ngpio = 8, + .request = asm28xx_gpio_request, + .set = asm28xx_gpio_set, + .get = asm28xx_gpio_get, + .direction_output = asm28xx_gpio_dirout, + .direction_input = asm28xx_gpio_dirin, + }, +}; + +static int __init asm28xx_gpio_init(void) +{ + int err = -ENODEV; + struct pci_dev *pdev = NULL; + const struct pci_device_id *ent; + u8 temp; + unsigned long flags; + int type; + + /* We look for our device - Asmedia 28XX and 18XX Bridge + * I don't know about a system with two such bridges, + * so we can assume that there is max. one device. + * + * We can't use plain pci_driver mechanism, + * as the device is really a multiple function device, + * main driver that binds to the pci_device is an bus + * driver and have to find & bind to the device this way. + */ + + for_each_pci_dev(pdev) { + ent = pci_match_id(pci_tbl, pdev); + if (ent) { + /* Because GPIO Registers only work on Upstream port. */ + type = pci_pcie_type(pdev); + if (type == PCI_EXP_TYPE_UPSTREAM) { + dev_info(&pdev->dev, "ASMEDIA-28xx/18xx Init Upstream detected\n"); + goto found; + } + } + } + goto out; + +found: + gp.pdev = pdev; + gp.chip.parent = &pdev->dev; + + spin_lock_init(&gp.lock); + + err = gpiochip_add_data(&gp.chip, &gp); + if (err) { + dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err); + goto out; + } + + pci_config_pm_runtime_get(pdev); + + /* Set PCI_CFG_Switch bit = 1,then we can access GPIO Registers. */ + spin_lock_irqsave(&gp.lock, flags); + pci_read_config_byte(pdev, ASM_REG_SWITCH, &temp); + temp |= ASM_REG_SWITCH_CTL; + pci_write_config_byte(pdev, ASM_REG_SWITCH, temp); + pci_read_config_byte(pdev, ASM_REG_SWITCH, &temp); + spin_unlock_irqrestore(&gp.lock, flags); + + pci_config_pm_runtime_put(pdev); + dev_err(&pdev->dev, "ASMEDIA-28xx/18xx Init SWITCH = 0x%x\n", temp); +out: + return err; +} + +static void __exit asm28xx_gpio_exit(void) +{ + unsigned long flags; + + pci_config_pm_runtime_get(gp.pdev); + + spin_lock_irqsave(&gp.lock, flags); + /* Set GPIO Registers to default value. */ + pci_write_config_byte(gp.pdev, ASM_GPIO_OUTPUT, ASM_GPIO_DEFAULT); + pci_write_config_byte(gp.pdev, ASM_GPIO_INPUT, ASM_GPIO_DEFAULT); + pci_write_config_byte(gp.pdev, ASM_GPIO_CTRL, ASM_GPIO_DEFAULT); + /* Clear PCI_CFG_Switch bit = 0,then we can't access GPIO Registers. */ + pci_write_config_byte(gp.pdev, ASM_REG_SWITCH, ASM_GPIO_DEFAULT); + spin_unlock_irqrestore(&gp.lock, flags); + pci_config_pm_runtime_put(gp.pdev); + + gpiochip_remove(&gp.chip); +} + +module_init(asm28xx_gpio_init); +module_exit(asm28xx_gpio_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Richard Hsu <Richard_Hsu@asmedia.com.tw>"); +MODULE_DESCRIPTION("ASMedia 28xx 18xx GPIO Driver");