diff mbox series

[v1,1/8] pinctrl: broxton: Provide Interrupt Status register offset

Message ID 20190723155633.65232-1-andriy.shevchenko@linux.intel.com
State New
Headers show
Series [v1,1/8] pinctrl: broxton: Provide Interrupt Status register offset | expand

Commit Message

Andy Shevchenko July 23, 2019, 3:56 p.m. UTC
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-broxton.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Mika Westerberg Aug. 6, 2019, 10:30 a.m. UTC | #1
On Tue, Jul 23, 2019 at 06:56:26PM +0300, Andy Shevchenko wrote:
> Since some of the GPIO controllers use different Interrupt Status offset,
> it make sense to provide it explicitly in the driver.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

For this and the rest of the patches in this series,

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
diff mbox series

Patch

diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index e2d4505d6747..2be7e414f803 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -15,8 +15,9 @@ 
 #include "pinctrl-intel.h"
 
 #define BXT_PAD_OWN	0x020
-#define BXT_HOSTSW_OWN	0x080
 #define BXT_PADCFGLOCK	0x060
+#define BXT_HOSTSW_OWN	0x080
+#define BXT_GPI_IS	0x100
 #define BXT_GPI_IE	0x110
 
 #define BXT_COMMUNITY(s, e)				\
@@ -24,6 +25,7 @@ 
 		.padown_offset = BXT_PAD_OWN,		\
 		.padcfglock_offset = BXT_PADCFGLOCK,	\
 		.hostown_offset = BXT_HOSTSW_OWN,	\
+		.is_offset = BXT_GPI_IS,		\
 		.ie_offset = BXT_GPI_IE,		\
 		.gpp_size = 32,                         \
 		.pin_base = (s),			\