From patchwork Thu Apr 25 10:20:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 1090665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="mk/R0U3R"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44qY9B6CDpz9s70 for ; Thu, 25 Apr 2019 20:20:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727282AbfDYKUa (ORCPT ); Thu, 25 Apr 2019 06:20:30 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33136 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfDYKUa (ORCPT ); Thu, 25 Apr 2019 06:20:30 -0400 Received: by mail-wr1-f67.google.com with SMTP id s18so4693180wrp.0 for ; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kDc3li6azRdBVeqSH107MAL3Z+IDS2Va16tVwCqx8k=; b=mk/R0U3R6hu9WlJ1qRU44gKZ8Tj7/3pU6xKmnMjtWxj5BLTYYB4g9bFbUzDBoUz9XM EX6pcFXj/CRhO3glYhUdGflRYsIuN/RBUYKB3nH+SgxJeuvVXqg3sTnBHNGoJ9t9r3TH lKUtdlREEOudPcffAs6gAf7a7IfnUlrxv1IPachgHXT7iVLTTSz6RkhFKkbTYSrWXDv3 QCC9szsbqluHQv6QxN0rsxhT0Waf2YcZLK8M45jRkbYiAB1TBR+Kq5dxC5hwyTv8/Kwv l1OOTOD1oATSUMqhtvMEsoIxIaXeI/HN/Dw30d+GmT5vF27wV2c+zg0guiwWl2l8YiSo CHCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kDc3li6azRdBVeqSH107MAL3Z+IDS2Va16tVwCqx8k=; b=sVb7FpZObLgfvjdm98Cou6ATqSH5tFLTDN0VwwdWHtSVPtFFZNpBR9WqoxKbLUDOI4 K9qY0fdLukZ8E79Z+RveBB8hvtFroXI7850mGex3WHgpK7uKplUnMBmO+3cJLB8+SQIh mGVZg4JSXN2c/ry8fnSxRokZMOHRJsbqFTwXgExtSHFIsZzqt7EAD+PyHdvGX7kJgUCi NNI2GYqnv3IH8qLUbPBTDcsEDEmRkJZHdhJwtlIqTfIj3o9XW3sY/ME+oiMDS3DvEUTn tDteL3/TzCIuoYXDSUWLjCrnF/EckWV2rbelvGInof2EHXXXAQIWRSq9SN7k7acjcG7U LN4Q== X-Gm-Message-State: APjAAAXA0V5WW9FU0WSB6j6aiss+Zco8/1Ety7cee2foCpOT5vpY7zhJ CXaERh8jeEn7NX2LnQrj7VC/qg== X-Google-Smtp-Source: APXvYqzKNRFPL+getGgdgv4uvvZu9g0FC1cRKZ4yZvoivavJp8Gr8ufQlvv1QIDT22Jk9wK7Uq6ffg== X-Received: by 2002:adf:ec4e:: with SMTP id w14mr2079300wrn.53.1556187627816; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id p18sm5611364wrp.38.2019.04.25.03.20.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:20:26 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Ard Biesheuvel , Masahisa Kojima , Linus Walleij , Marc Zyngier , Graeme Gregory Subject: [RFC PATCH 3/3] gpio: mb86s70: enable ACPI and irqchip support Date: Thu, 25 Apr 2019 12:20:20 +0200 Message-Id: <20190425102020.21533-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In order to support this GPIO block in combination with an EXIU interrupt controller on ACPI systems such as Socionext SynQuacer, add the enumeration boilerplate, and add the EXIU irqchip handling to the probe path. Also, make the clock handling conditonal on non-ACPI enumeration, since ACPI handles this internally. Signed-off-by: Ard Biesheuvel --- drivers/gpio/Kconfig | 4 ++ drivers/gpio/gpio-mb86s7x.c | 58 +++++++++++++++++--- 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3f50526a771f..2c2773ea9627 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -315,6 +315,10 @@ config GPIO_MB86S7X help Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs. +config GPIO_MB86S7X_ACPI + def_bool y + depends on ACPI && ARCH_SYNQUACER + config GPIO_MENZ127 tristate "MEN 16Z127 GPIO support" depends on MCB diff --git a/drivers/gpio/gpio-mb86s7x.c b/drivers/gpio/gpio-mb86s7x.c index 3134c0d2bfe4..d254783f7e71 100644 --- a/drivers/gpio/gpio-mb86s7x.c +++ b/drivers/gpio/gpio-mb86s7x.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,6 +28,8 @@ #include #include +#include "gpiolib.h" + /* * Only first 8bits of a register correspond to each pin, * so there are 4 registers for 32 pins. @@ -44,6 +47,8 @@ struct mb86s70_gpio_chip { spinlock_t lock; }; +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc); + static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) { struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); @@ -143,6 +148,12 @@ static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) spin_unlock_irqrestore(&gchip->lock, flags); } +static bool mb86s70_gpio_have_acpi(struct platform_device *pdev) +{ + return IS_ENABLED(CONFIG_GPIO_MB86S7X_ACPI) && + ACPI_COMPANION(&pdev->dev); +} + static int mb86s70_gpio_probe(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip; @@ -160,13 +171,15 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) if (IS_ERR(gchip->base)) return PTR_ERR(gchip->base); - gchip->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(gchip->clk)) - return PTR_ERR(gchip->clk); + if (!mb86s70_gpio_have_acpi(pdev)) { + gchip->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(gchip->clk)) + return PTR_ERR(gchip->clk); - ret = clk_prepare_enable(gchip->clk); - if (ret) - return ret; + ret = clk_prepare_enable(gchip->clk); + if (ret) + return ret; + } spin_lock_init(&gchip->lock); @@ -182,21 +195,39 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) gchip->gc.parent = &pdev->dev; gchip->gc.base = -1; + if (mb86s70_gpio_have_acpi(pdev)) { + ret = exiu_acpi_init(pdev, &gchip->gc); + if (ret) { + dev_err(&pdev->dev, "couldn't register gpio irqchip\n"); + return ret; + } + } + ret = gpiochip_add_data(&gchip->gc, gchip); if (ret) { dev_err(&pdev->dev, "couldn't register gpio driver\n"); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); + return ret; } - return ret; + if (mb86s70_gpio_have_acpi(pdev)) + acpi_gpiochip_request_interrupts(&gchip->gc); + + return 0; } static int mb86s70_gpio_remove(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); + if (gchip->gc.irq.domain) { + acpi_gpiochip_free_interrupts(&gchip->gc); + irq_domain_remove(gchip->gc.irq.domain); + } gpiochip_remove(&gchip->gc); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); return 0; } @@ -207,10 +238,19 @@ static const struct of_device_id mb86s70_gpio_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); +#ifdef CONFIG_ACPI +static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = { + { "SCX0007" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids); +#endif + static struct platform_driver mb86s70_gpio_driver = { .driver = { .name = "mb86s70-gpio", .of_match_table = mb86s70_gpio_dt_ids, + .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids), }, .probe = mb86s70_gpio_probe, .remove = mb86s70_gpio_remove,