| Message ID | 20180725191546.3416-1-wsa+renesas@sang-engineering.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: sh-pfc: r8a77965: Add SATA pins, groups and functions | expand |
On Wed, Jul 25, 2018 at 9:15 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch adds SATA0 pin, group and function to the R8A77965 SoC. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > [wsa: rebased to upstream base] > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in sh-pfc-for-v4.20. Gr{oetje,eeting}s, Geert
On Wed, Jul 25, 2018 at 09:15:46PM +0200, Wolfram Sang wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch adds SATA0 pin, group and function to the R8A77965 SoC. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > [wsa: rebased to upstream base] > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Wolfram, On Wed, Jul 25, 2018 at 9:15 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch adds SATA0 pin, group and function to the R8A77965 SoC. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > [wsa: rebased to upstream base] > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c > @@ -3664,6 +3685,11 @@ static const char * const du_groups[] = { > "du_disp", > }; > > +static const char * const sata0_groups[] = { > + "sata0_devslp_a", > + "sata0_devslp_b", > +}; > + Moving the above hunk to its correct destination while applying... > static const char * const hscif0_groups[] = { > "hscif0_data", > "hscif0_clk", Gr{oetje,eeting}s, Geert
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index cfd7de67e3e3..e43a5b39784c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -2907,6 +2907,25 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - SATA --------------------------------------------------------------------*/ +static const unsigned int sata0_devslp_a_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(6, 16), +}; + +static const unsigned int sata0_devslp_a_mux[] = { + SATA_DEVSLP_A_MARK, +}; + +static const unsigned int sata0_devslp_b_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(4, 6), +}; + +static const unsigned int sata0_devslp_b_mux[] = { + SATA_DEVSLP_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3579,6 +3598,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3664,6 +3685,11 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const sata0_groups[] = { + "sata0_devslp_a", + "sata0_devslp_b", +}; + static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -3999,6 +4025,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2),