| Message ID | 20180725124208.62991-1-andriy.shevchenko@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] pinctrl: intel: Do pin translation when lock IRQ | expand |
On Wed, Jul 25, 2018 at 03:42:08PM +0300, Andy Shevchenko wrote: > Default GPIOLIB callbacks for request and release IRQ do not do a GPIO > to pin translation which is necessary for Intel hardware, such as Intel > Cannonlake. Absence of the translation prevents some pins to be locked > as IRQ due to direction check. Introduce own callbacks to make > translation possible to avoid above issue. > > Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") > Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Jul 25, 2018 at 2:42 PM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > Default GPIOLIB callbacks for request and release IRQ do not do a GPIO > to pin translation which is necessary for Intel hardware, such as Intel > Cannonlake. Absence of the translation prevents some pins to be locked > as IRQ due to direction check. Introduce own callbacks to make > translation possible to avoid above issue. > > Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") > Cc: Mika Westerberg <mika.westerberg@linux.intel.com> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Patch applied with Mika's ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 3d0bd7b99725..d023b64825d0 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -872,6 +872,34 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset, return -EINVAL; } +static int intel_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + int pin; + + pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); + if (pin >= 0) { + if (gpiochip_lock_as_irq(gc, pin)) { + dev_err(pctrl->dev, "unable to lock HW IRQ %d for IRQ\n", + pin); + return -EINVAL; + } + } + return 0; +} + +static void intel_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + int pin; + + pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); + if (pin >= 0) + gpiochip_unlock_as_irq(gc, pin); +} + static void intel_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1087,6 +1115,8 @@ static irqreturn_t intel_gpio_irq(int irq, void *data) static struct irq_chip intel_gpio_irqchip = { .name = "intel-gpio", + .irq_request_resources = intel_gpio_irq_reqres, + .irq_release_resources = intel_gpio_irq_relres, .irq_enable = intel_gpio_irq_enable, .irq_ack = intel_gpio_irq_ack, .irq_mask = intel_gpio_irq_mask,
Default GPIOLIB callbacks for request and release IRQ do not do a GPIO to pin translation which is necessary for Intel hardware, such as Intel Cannonlake. Absence of the translation prevents some pins to be locked as IRQ due to direction check. Introduce own callbacks to make translation possible to avoid above issue. Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/pinctrl/intel/pinctrl-intel.c | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)