From patchwork Tue Dec 12 17:43:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 847569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="of+G3ZCt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yx6dn5kNPz9sBW for ; Wed, 13 Dec 2017 04:44:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752336AbdLLRo3 (ORCPT ); Tue, 12 Dec 2017 12:44:29 -0500 Received: from mail-it0-f67.google.com ([209.85.214.67]:45520 "EHLO mail-it0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752323AbdLLRo1 (ORCPT ); Tue, 12 Dec 2017 12:44:27 -0500 Received: by mail-it0-f67.google.com with SMTP id z6so311403iti.4 for ; Tue, 12 Dec 2017 09:44:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=ENuRXCf/abWVkhvgfKCqdGYracy59keZzDcI8S9+qGw=; b=of+G3ZCtL+sqXBh7TPq2pb8CuOJG7pJQk1RrJ1FwwPKgF+R87GqWa56jHWU7sJxsWu O5/q86pFUG5pG3um/y3VYU0zyoC8dve2OUcx1m4rwP7MIwEyiCjU3gnZ3J5RviuyoNyZ oZ/iwwPkcXLxQe5mzlBPmdRx1gKRyA8c+c62U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ENuRXCf/abWVkhvgfKCqdGYracy59keZzDcI8S9+qGw=; b=pBh232OtCIjiZ91DOT3O5guT7BbceJFO1cFEkR0G4yt1gWPP4UwJNYpmIE+6BmHvVw q8n6wYN+v69B/OgNBy5GrUjiyQa2iXOh2MTKVpfgF97XAGqq6PoumNih4oOLdFCQZUQq Z7taPAzD5RYZn7FuJaLXT6tH0XwpUTVLre++2Bpwn6TIWdSHBBqPzdOjEjm7aJ+GPECX z3RiDoTSZip1wY7jt2R2ZgOqOiukDKX+zTFs0qRazqH3+dKUMzGD9vdWqakvqhdGKBBE wNg6iZkloqzNjHLpIiYb1KHo7oMizEIEsGkhlq7OB0vQdsOxPFPYnP5je4HkfWIifCO/ zdkg== X-Gm-Message-State: AKGB3mJBR932Bghn2GJscXdWLu4J8ZdTYwpa9VZc61F5msTxaVgJoGQl W8ZTwHvyCU4FYGensmgwDhJIGg== X-Google-Smtp-Source: ACJfBotC2Sudknu3IQ9uVeY080kxNahNSDfJCniBc6BYHyviEqS8VygxHHlCIbi8utM2Ovsvs+rPaQ== X-Received: by 10.107.102.26 with SMTP id a26mr4144078ioc.187.1513100666520; Tue, 12 Dec 2017 09:44:26 -0800 (PST) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id d3sm32253itj.34.2017.12.12.09.44.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Dec 2017 09:44:24 -0800 (PST) From: Brian Norris To: Linus Walleij , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Doug Anderson , Brian Norris Subject: [PATCH] pinctrl: rockchip: enable clock when reading pin direction register Date: Tue, 12 Dec 2017 09:43:43 -0800 Message-Id: <20171212174343.192017-1-briannorris@chromium.org> X-Mailer: git-send-email 2.15.1.424.g9478a66081-goog Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We generally leave the GPIO clock disabled, unless an interrupt is requested or we're accessing IO registers. We forgot to do this for the ->get_direction() callback, which means we can sometimes [1] get incorrect results [2] from, e.g., /sys/kernel/debug/gpio. Enable the clock, so we get the right results! [1] Sometimes, because many systems have 1 or mor interrupt requested on each GPIO bank, so they always leave their clock on. [2] Incorrect, meaning the register returns 0, and so we interpret that as "input". Signed-off-by: Brian Norris Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 2ba17548ad5b..073de6a9ed34 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2014,8 +2014,16 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) { struct rockchip_pin_bank *bank = gpiochip_get_data(chip); u32 data; + int ret; + ret = clk_enable(bank->clk); + if (ret < 0) { + dev_err(bank->drvdata->dev, + "failed to enable clock for bank %s\n", bank->name); + return ret; + } data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); + clk_disable(bank->clk); return !(data & BIT(offset)); }