From patchwork Thu Mar 23 16:51:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 742786 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vpt116F9cz9s82 for ; Fri, 24 Mar 2017 03:53:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Dnm2QG1w"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965695AbdCWQv2 (ORCPT ); Thu, 23 Mar 2017 12:51:28 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:35406 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965681AbdCWQvN (ORCPT ); Thu, 23 Mar 2017 12:51:13 -0400 Received: by mail-wr0-f169.google.com with SMTP id u1so17510722wra.2 for ; Thu, 23 Mar 2017 09:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uZuiB400ml//jXF24ets7QvAB9G/3bo4NYUr68nS6qg=; b=Dnm2QG1woqLr/QV6qBIv22Tk5/Qi2rGnOe0LF1hkLc3cux0ULGU5HEROTRttIas9/5 Dfb4FSzv5GDyiS3O6c1MIdqRcLpb35yMvEyBz3yXcmn10nxIQoR590fkCMSR7X4XtNEC DYPLw0kr8y3wjszSsMLZrDe1qnDd3wmptJuZcDcQugTpd0Wpjx5CPacg/v9Oo7cUsZtX +uayByDcacFum4WfMUyAmuubG7MtzA03I/xDz44GrGfbdEyRs3tYBZ5u6LTHquRz/j3e X3hHIPkmEtUZKT0K3Kg+z4mk6ybV3wS3KGYFdEKi7G7oLp1a30hEFcDsVpPHLxXDaLUG Ej/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uZuiB400ml//jXF24ets7QvAB9G/3bo4NYUr68nS6qg=; b=Ut35IZOeuT7pPGtVKHkMzCGXeZu4KPD0N3Ivp/1p8mCg+ALNp65LX+YnyXpB38QFsi CIVm/rRpJyB1LFaAEte+itGZyVfbDFaPJqJ2rY7nNTAX5Ca6R4pXABLN3JTfAoMi8c0/ 5fST49+CKs+w/E010E987fh9f+rj93z07lWK1RQDvufVaXvYJB9lf/eXXzIF3PbQxkEI ZZijiEJfauyNMIx/eqa2790c9j/VO2wRWtVpWR1Z8Dwyzz9Az0QHpZI9wjHHJFDRuws9 vG3cvU0HCU/cd5WXSy4hpA/XVjcPdcDPF8fmZY1Qh/oRVlRuy3JN+ADEj7ExxdvbobAW P9TQ== X-Gm-Message-State: AFeK/H24GigkrMX0RBcESYpCW6/HMgf/I8+KMxZL67qyeACQAZsXmHK89TlVdFHa+D/lvEHe X-Received: by 10.223.164.150 with SMTP id g22mr3854368wrb.92.1490287871828; Thu, 23 Mar 2017 09:51:11 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id e129sm5061893wma.13.2017.03.23.09.51.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Mar 2017 09:51:11 -0700 (PDT) From: Jerome Brunet To: Linus Walleij , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] ARM64: dts: meson-gxl: add i2s output pins Date: Thu, 23 Mar 2017 17:51:00 +0100 Message-Id: <20170323165101.29262-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170323165101.29262-1-jbrunet@baylibre.com> References: <20170323165101.29262-1-jbrunet@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 62 ++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index fe11b5fc61f7..88ad3490c124 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -124,6 +124,20 @@ function = "pwm_ao_b"; }; }; + + i2s_out_ch23_ao_pins: i2s_out_ch23_ao { + mux { + groups = "i2s_out_ch23_ao"; + function = "i2s_out_ao"; + }; + }; + + i2s_out_ch45_ao_pins: i2s_out_ch45_ao { + mux { + groups = "i2s_out_ch45_ao"; + function = "i2s_out_ao"; + }; + }; }; }; @@ -297,6 +311,54 @@ function = "hdmi_i2c"; }; }; + + i2s_am_clk_pins: i2s_am_clk { + mux { + groups = "i2s_am_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_ao_clk_pins: i2s_out_ao_clk { + mux { + groups = "i2s_out_ao_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_lr_clk_pins: i2s_out_lr_clk { + mux { + groups = "i2s_out_lr_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_ch01_pins: i2s_out_ch01 { + mux { + groups = "i2s_out_ch01"; + function = "i2s_out"; + }; + }; + i2sout_ch23_z_pins: i2sout_ch23_z { + mux { + groups = "i2sout_ch23_z"; + function = "i2s_out"; + }; + }; + + i2sout_ch45_z_pins: i2sout_ch45_z { + mux { + groups = "i2sout_ch45_z"; + function = "i2s_out"; + }; + }; + + i2sout_ch67_z_pins: i2sout_ch67_z { + mux { + groups = "i2sout_ch67_z"; + function = "i2s_out"; + }; + }; }; eth-phy-mux {