From patchwork Tue Jan 17 16:19:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 716287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v2wNN3yN9z9srY for ; Wed, 18 Jan 2017 03:21:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750866AbdAQQU2 (ORCPT ); Tue, 17 Jan 2017 11:20:28 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:51088 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750932AbdAQQU0 (ORCPT ); Tue, 17 Jan 2017 11:20:26 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v0HGJtC9024957; Tue, 17 Jan 2017 10:19:55 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v0HGJo4g028686; Tue, 17 Jan 2017 10:19:50 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 17 Jan 2017 10:19:49 -0600 Received: from ula0393675.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v0HGJd2v016436; Tue, 17 Jan 2017 10:19:45 -0600 From: Keerthy To: CC: , , , , , Subject: [PATCH V3 1/5] gpio: davinci: Remove gpio2regs function to accommodate multi instances Date: Tue, 17 Jan 2017 21:49:11 +0530 Message-ID: <1484669955-5349-2-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1484669955-5349-1-git-send-email-j-keerthy@ti.com> References: <1484669955-5349-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org gpio2regs is written making an assumption that driver supports only one instance of gpio controller. Removing this and adding a generic array so as to support multiple instances of gpio controllers. Signed-off-by: Keerthy Reviewed-by: Grygorii Strashko --- Changes in v2: * Added a comment to explain divide by 2 logic for register sets. drivers/gpio/gpio-davinci.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 163f81e..bb47de3 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -43,25 +43,7 @@ struct davinci_gpio_regs { #define MAX_LABEL_SIZE 20 static void __iomem *gpio_base; - -static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) -{ - void __iomem *ptr; - - if (gpio < 32 * 1) - ptr = gpio_base + 0x10; - else if (gpio < 32 * 2) - ptr = gpio_base + 0x38; - else if (gpio < 32 * 3) - ptr = gpio_base + 0x60; - else if (gpio < 32 * 4) - ptr = gpio_base + 0x88; - else if (gpio < 32 * 5) - ptr = gpio_base + 0xb0; - else - ptr = NULL; - return ptr; -} +static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) { @@ -262,7 +244,7 @@ static int davinci_gpio_probe(struct platform_device *pdev) #endif spin_lock_init(&chips[i].lock); - regs = gpio2regs(base); + regs = gpio_base + offset_array[i]; if (!regs) return -ENXIO; chips[i].regs = regs; @@ -417,7 +399,9 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct davinci_gpio_regs __iomem *g = gpio2regs(hw); + struct davinci_gpio_controller *chips = + (struct davinci_gpio_controller *)d->host_data; + struct davinci_gpio_regs __iomem *g = chips[hw / 32].regs; irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, "davinci_gpio"); @@ -554,7 +538,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) irq_chip->irq_set_type = gpio_irq_type_unbanked; /* default trigger: both edges */ - g = gpio2regs(0); + g = chips[0].regs; writel_relaxed(~0, &g->set_falling); writel_relaxed(~0, &g->set_rising); @@ -573,8 +557,11 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) * then chain through our own handler. */ for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { - /* disabled by default, enabled only as needed */ - g = gpio2regs(gpio); + /* disabled by default, enabled only as needed + * There are register sets for 32 GPIOs. 2 banks of 16 + * GPIOs are covered by each set of registers hence divide by 2 + */ + g = chips[bank / 2].regs; writel_relaxed(~0, &g->clr_falling); writel_relaxed(~0, &g->clr_rising);