| Message ID | 1483744980-25898-2-git-send-email-ddaney.cavm@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Sat, Jan 7, 2017 at 12:22 AM, David Daney <ddaney.cavm@gmail.com> wrote: > From: David Daney <david.daney@cavium.com> > > Signed-off-by: David Daney <david.daney@cavium.com> (...) > +Optional Properties: > +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. > +- interrupt-controller: Marks the device node as an interrupt controller. > +- #interrupt-cells: Must be present and have value of 2 if > + "interrupt-controller" is present. > + - First cell is the GPIO pin number relative to the controller. > + - Second cell is triggering flags as defined in interrupts.txt. AFAICT this device has an optional list of interrupts as well? One per pin even? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 01/09/2017 11:36 AM, Linus Walleij wrote: > On Sat, Jan 7, 2017 at 12:22 AM, David Daney <ddaney.cavm@gmail.com> wrote: > >> From: David Daney <david.daney@cavium.com> >> >> Signed-off-by: David Daney <david.daney@cavium.com> > (...) > >> +Optional Properties: >> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. >> +- interrupt-controller: Marks the device node as an interrupt controller. >> +- #interrupt-cells: Must be present and have value of 2 if >> + "interrupt-controller" is present. >> + - First cell is the GPIO pin number relative to the controller. >> + - Second cell is triggering flags as defined in interrupts.txt. > > AFAICT this device has an optional list of interrupts as well? > One per pin even? I'm not sure I understand your question. The GPIO hardware supports an interrupt on each pin. The underlying interrupt mechanism is via PCI MSI-X, which are fully discoverable by the driver, so lack of device tree binding for the these underlying MSI-X is fully appropriate. On the other hand, users of the GPIO interrupt pins need this "interrupt-controller" and "#interrupt-cells" to be able to properly find and configure the proper interrupts. I said the "interrupt-controller" property was optional, because some systems don't use GPIO interrupts and can function without specifying that it is also an interrupt controller. > > Yours, > Linus Walleij > -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jan 06, 2017 at 03:22:58PM -0800, David Daney wrote: > From: David Daney <david.daney@cavium.com> > > Signed-off-by: David Daney <david.daney@cavium.com> > --- > .../devicetree/bindings/gpio/gpio-thunderx.txt | 27 ++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jan 9, 2017 at 8:44 PM, David Daney <ddaney@caviumnetworks.com> wrote: > On 01/09/2017 11:36 AM, Linus Walleij wrote: >>> +Optional Properties: >>> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding >>> is used. >>> +- interrupt-controller: Marks the device node as an interrupt >>> controller. >>> +- #interrupt-cells: Must be present and have value of 2 if >>> + "interrupt-controller" is present. >>> + - First cell is the GPIO pin number relative to the controller. >>> + - Second cell is triggering flags as defined in interrupts.txt. >> >> >> AFAICT this device has an optional list of interrupts as well? >> One per pin even? > > I'm not sure I understand your question. > > The GPIO hardware supports an interrupt on each pin. The underlying > interrupt mechanism is via PCI MSI-X, which are fully discoverable by the > driver, so lack of device tree binding for the these underlying MSI-X is > fully appropriate. Sorry I guess I'm just ignorant about how PCI works, that has never been my strongest subject admittedly. So what you're saying is that PCI devices do not need specifying interrupts not interrupt parents in the device tree? That's fine then. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt new file mode 100644 index 0000000..3f883ae --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt @@ -0,0 +1,27 @@ +Cavium ThunderX/OCTEON-TX GPIO controller bindings + +Required Properties: +- reg: The controller bus address. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Must be 2. + - First cell is the GPIO pin number relative to the controller. + - Second cell is a standard generic flag bitfield as described in gpio.txt. + +Optional Properties: +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Must be present and have value of 2 if + "interrupt-controller" is present. + - First cell is the GPIO pin number relative to the controller. + - Second cell is triggering flags as defined in interrupts.txt. + +Example: + +gpio_6_0: gpio@6,0 { + compatible = "cavium,thunder-8890-gpio"; + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +};