From patchwork Fri Jun 17 12:03:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 636970 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rWJpW6Mfcz9t1r for ; Fri, 17 Jun 2016 22:04:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161057AbcFQMEr (ORCPT ); Fri, 17 Jun 2016 08:04:47 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1476 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933546AbcFQMEp (ORCPT ); Fri, 17 Jun 2016 08:04:45 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 17 Jun 2016 05:04:07 -0700 Received: from HQHUB102.nvidia.com ([172.20.187.25]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 17 Jun 2016 05:01:06 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 17 Jun 2016 05:01:06 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQHUB102.nvidia.com (172.20.187.25) with Microsoft SMTP Server (TLS) id 8.3.406.0; Fri, 17 Jun 2016 05:04:44 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 12:04:44 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 17 Jun 2016 12:04:44 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.108]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,5,8150) id ; Fri, 17 Jun 2016 05:04:44 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot , Wolfram Sang , Linus Walleij , Rob Herring , Mark Rutland CC: , , , , , Jon Hunter Subject: [RFC PATCH 11/13] arm64: tegra: Add SOR power-domain node Date: Fri, 17 Jun 2016 13:03:45 +0100 Message-ID: <1466165027-17917-12-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> References: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for SOR and DPAUX nodes that are dependent on this power-domain. Please note that although neither the SOR or DPAUX drivers currently support runtime power-management, by populating the power-domain node the SOR power-domain will be turned on before probing SOR or DPAUX devices and kept on while the devices are bound. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ebf44f4059f8..94f780b43037 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -34,6 +34,7 @@ clock-names = "dpaux", "parent"; resets = <&tegra_car 207>; reset-names = "dpaux"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -154,6 +155,7 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -168,6 +170,7 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -180,6 +183,7 @@ clock-names = "dpaux", "parent"; resets = <&tegra_car 181>; reset-names = "dpaux"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -592,6 +596,20 @@ resets = <&tegra_car 198>; #power-domain-cells = <0>; }; + + pd_sor: sor { + clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_DSIA>, + <&tegra_car TEGRA210_CLK_DSIB>, + <&tegra_car TEGRA210_CLK_MIPI_CAL>, + <&tegra_car TEGRA210_CLK_DPAUX>; + resets = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_DSIA>, + <&tegra_car TEGRA210_CLK_DSIB>, + <&tegra_car TEGRA210_CLK_DPAUX>, + <&tegra_car TEGRA210_CLK_MIPI_CAL>; + #power-domain-cells = <0>; + }; }; };