From patchwork Thu Mar 31 15:09:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 604189 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qbSgG3M8dz9s4n for ; Fri, 1 Apr 2016 02:12:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=d3MGgOUj; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757188AbcCaPJ4 (ORCPT ); Thu, 31 Mar 2016 11:09:56 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36243 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757342AbcCaPJy (ORCPT ); Thu, 31 Mar 2016 11:09:54 -0400 Received: by mail-wm0-f68.google.com with SMTP id 20so24487653wmh.3; Thu, 31 Mar 2016 08:09:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hFeoSfqH87nM48ZzQxc9M48VNm9wLa2O70RiEh1af8Q=; b=d3MGgOUjCGmJzX/eGjMeSZb3torQGo86cYR6ncoTHOplgEWkXxbtDIsyn8e/AL6EgN uGR/bQlu/VYvj+rTCmHPxVkJ/pjwHWyjB6xFudy9brA9LWbfNz33Cy8+3zhFxap3gZVe q4NiCzt8n+7XpOcM609SzYz1REmdVpsjrB3PIvd/lnanHW65Q7UhM6aYAh69griGL/4z 0A36anzwyYv8YQh9ZDzzAeKBDesijvYV6J+pEdpjsyGqIdhpbkmdGqgOvbuYbyeknHN5 6ybCfceVfhxXieNK+/QBP6D16rCI8MhKk2QVfFwaSrIFAbTvFIwoFf0jRGm1Qs0RjJyv DhJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hFeoSfqH87nM48ZzQxc9M48VNm9wLa2O70RiEh1af8Q=; b=YNVXShj4BbDDm9dP180DE35KDDKfqvJKHcr3p3myEIuynHSUt3mZPFbCHnwOwOQEyw df+V9bwLFZMEKMeGYKhVt5iYMuWxLP7bFiFMIvDGk4ZSWLJuN690ZZQIKsUQmR3Cy/Jp S6m7pR9yAacCbA4XMqLJXXRYsnJxQnrKULhi9/E551sIDq4Q5MG33CUd8XSprhH21rzs zHBSU3XsU/3/xkEeFA9LsFtzKKnr4ndq++Ewk1T68Pi/77rdmwMCFQ7vBpSyufc6Crd+ 4GyLDsD9FBzisyAU9XLjBRP45NzM50EIwnFjyPUG4EbMGGkJMcdo1oZt1RCvSW3hbI9H lMng== X-Gm-Message-State: AD7BkJL6hWgEgEhlvRJfiWTL2hyL/lwArQHjqqYRQKH+sEZlxaoDU7UnV3ThISZArefhIg== X-Received: by 10.28.104.131 with SMTP id d125mr303691wmc.99.1459436993106; Thu, 31 Mar 2016 08:09:53 -0700 (PDT) Received: from lmecul0520.st.com. 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[77.154.204.241]) by smtp.gmail.com with ESMTPSA id i5sm9505781wjx.15.2016.03.31.08.09.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 31 Mar 2016 08:09:52 -0700 (PDT) From: Maxime Coquelin To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com, lee.jones@linaro.org Subject: [PATCH v2 6/9] pinctrl: Add IRQ support to STM32 gpios Date: Thu, 31 Mar 2016 17:09:36 +0200 Message-Id: <1459436979-17275-7-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459436979-17275-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1459436979-17275-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by: Maxime Coquelin --- drivers/pinctrl/stm32/Kconfig | 1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 68 +++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index 0f28841b2332..b5cac5bfd0cd 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -6,6 +6,7 @@ config PINCTRL_STM32 select PINMUX select GENERIC_PINCONF select GPIOLIB + select MFD_SYSCON config PINCTRL_STM32F429 bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 8deb566ed4cd..f2fa717894dc 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -20,6 +22,7 @@ #include #include #include +#include #include #include @@ -77,6 +80,9 @@ struct stm32_pinctrl { struct stm32_gpio_bank *banks; unsigned nbanks; const struct stm32_pinctrl_match_data *match_data; + struct irq_domain *domain; + struct regmap *regmap; + struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; }; static inline int stm32_gpio_pin(int gpio) @@ -174,6 +180,22 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip, return 0; } + +static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct stm32_pinctrl *pctl = dev_get_drvdata(chip->parent); + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int irq; + + regmap_field_write(pctl->irqmux[offset], bank->range.id); + + irq = irq_create_mapping(pctl->domain, offset); + if (!irq) + return -ENXIO; + + return irq; +} + static struct gpio_chip stm32_gpio_template = { .request = stm32_gpio_request, .free = stm32_gpio_free, @@ -181,6 +203,7 @@ static struct gpio_chip stm32_gpio_template = { .set = stm32_gpio_set, .direction_input = stm32_gpio_direction_input, .direction_output = stm32_gpio_direction_output, + .to_irq = stm32_gpio_to_irq, }; /* Pinctrl functions */ @@ -704,6 +727,47 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, return 0; } +static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, + struct stm32_pinctrl *pctl) +{ + struct device_node *np = pdev->dev.of_node, *parent; + struct device *dev = &pdev->dev; + struct regmap *rm; + int offset, ret, i; + + parent = of_irq_find_parent(np); + if (!parent) + return -ENXIO; + + pctl->domain = irq_find_host(parent); + if (!pctl->domain) + return -ENXIO; + + pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(pctl->regmap)) + return PTR_ERR(pctl->regmap); + + rm = pctl->regmap; + + ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); + if (ret) + return ret; + + for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { + struct reg_field mux; + + mux.reg = offset + (i / 4) * 4; + mux.lsb = (i % 4) * 4; + mux.msb = mux.lsb + 3; + + pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); + if (IS_ERR(pctl->irqmux[i])) + return PTR_ERR(pctl->irqmux[i]); + } + + return 0; +} + static int stm32_pctrl_build_state(struct platform_device *pdev) { struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); @@ -796,6 +860,10 @@ int stm32_pctl_probe(struct platform_device *pdev) } } + ret = stm32_pctrl_dt_setup_irq(pdev, pctl); + if (ret) + return ret; + pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), GFP_KERNEL); if (!pins)