Message ID | 1438000918-9026-3-git-send-email-maxime.ripard@free-electrons.com |
---|---|
State | New |
Headers | show |
On Mon, Jul 27, 2015 at 2:41 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > The current DTs were setting the cell size to 2, but used the default xlate > function that was assuming an interrupt cell size of 1, leading to the > second part of the cell (the flags) being ignored, while we were having an > inconsistent binding between the interrupts and gpio (that could also be > used as interrupts). > > That "binding" doesn't work either with newer SoCs that have multiple irq > banks. > > Now that we fixed the pinctrl driver to handle this like it should always > have been handled, convert the DT users, and while we're at it, remove the > size-cells property of PIO that is completely useless. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> I guess this will be merged through ARM SoC? If you want me to carry it in pinctrl and you're *certain* it will not collide with something else coming in from ARM SoC then tell me ... prefer to even have ARM SoC maintainers ACK on this actually. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jul 27, 2015 at 02:58:29PM +0200, Linus Walleij wrote: > On Mon, Jul 27, 2015 at 2:41 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > > The current DTs were setting the cell size to 2, but used the default xlate > > function that was assuming an interrupt cell size of 1, leading to the > > second part of the cell (the flags) being ignored, while we were having an > > inconsistent binding between the interrupts and gpio (that could also be > > used as interrupts). > > > > That "binding" doesn't work either with newer SoCs that have multiple irq > > banks. > > > > Now that we fixed the pinctrl driver to handle this like it should always > > have been handled, convert the DT users, and while we're at it, remove the > > size-cells property of PIO that is completely useless. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Reviewed-by: Hans de Goede <hdegoede@redhat.com> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > I guess this will be merged through ARM SoC? > > If you want me to carry it in pinctrl and you're *certain* it > will not collide with something else coming in from ARM SoC > then tell me ... prefer to even have ARM SoC maintainers > ACK on this actually. I'll merge it through my tree (and then arm-soc). Thanks! Maxime
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 61c03d1fe530..710a0531953e 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -713,8 +713,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 514f159a14d4..9303fa035b0e 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -93,7 +93,7 @@ compatible = "chipone,icn8318"; reg = <0x40>; interrupt-parent = <&pio>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ pinctrl-names = "default"; pinctrl-0 = <&ts_wake_pin_p66>; wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 54b097830434..c58d5a62605f 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -475,8 +475,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; i2c0_pins_a: i2c0@0 { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 008047a018cf..2541412cabb0 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -599,8 +599,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 4611e2f5a99e..70d0f85a636d 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -181,7 +181,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index f32f6f20d923..1e6bd360dac0 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -178,7 +178,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 6a63f30c9a69..d3497a51f0c4 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -794,8 +794,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 7abd0ae3143d..f93105709680 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -339,8 +339,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 {