From patchwork Sat May 9 07:53:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 470294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 89760140281 for ; Sat, 9 May 2015 17:59:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Pb6sC8ey; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753875AbbEIHyh (ORCPT ); Sat, 9 May 2015 03:54:37 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:35885 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753828AbbEIHyY (ORCPT ); Sat, 9 May 2015 03:54:24 -0400 Received: by wizk4 with SMTP id k4so53147418wiz.1; Sat, 09 May 2015 00:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vseM6ZohiqQVk1Svl/D7jRnhl5I3X2BB1fd85oglX9Q=; b=Pb6sC8eyWDk+CydHTuIhO4LJsrTDsWLJFJPbA1JdXBe3nv8Fi56v2duZHetphEVSVd diMeiTo+6goCUaVoSlRRTKNr0DMe2HVhwZtIViOq8Sr9yrUoA1I5dy/yadk6CPZsD/oz biH+fGCr5q2PPTugvBMK2nxtMRHp7vVrSawC/X3aGI6g+KS4ybu+jD4etP/61aLRt4iC Un9VAXRiM4/FkcoblQzbolYOs2loyt549+o/kPZAxGzll/yv6nOXagtF/NnvoBD8AtYY 0lnMGg+Wyfqdh3snkQB6emOQarJzHHtv3i01Xhoqlh9HsGCjZy7YwMDGlYNn5/UAubFq 1s6Q== X-Received: by 10.180.160.145 with SMTP id xk17mr3198718wib.85.1431158062444; Sat, 09 May 2015 00:54:22 -0700 (PDT) Received: from lmecul0520.st.com. (213.143.7.84.rev.sfr.net. [84.7.143.213]) by mx.google.com with ESMTPSA id z12sm12098020wjq.12.2015.05.09.00.54.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 09 May 2015 00:54:21 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano , joe@perches.com, Vladimir Zapolskiy , lee.jones@linaro.org, Daniel Thompson Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com, Nicolae Rosia , Kamil Lulko Subject: [PATCH v8 06/16] dt-bindings: Document the STM32 reset bindings Date: Sat, 9 May 2015 09:53:48 +0200 Message-Id: <1431158038-3813-7-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation of device tree bindings for the STM32 reset controller. Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt new file mode 100644 index 0000000..333080c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt @@ -0,0 +1,50 @@ +STMicroelectronics STM32 Peripheral Reset Controller +==================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +documents the reset part. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32-rcc" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +example: + +rcc: reset@40023800 { + #reset-cells = <1>; + compatible = "st,stm32-rcc"; + reg = <0x40023800 0x400>; +}; + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. +For example, for CRC reset: + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 + +To simplify the usagen and to share bit definition with the clock driver of +the RCC IP, macros are available to generate the index in human-readble +format. + +For STM32F4 series, the macro are available here: + - include/dt-bindings/mfd/stm32f4-rcc.h + +example: + + timer2 { + resets = <&rcc STM32F4_APB1_RESET(TIM2)>; + }; + +