From patchwork Thu Apr 2 09:55:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 457585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8C502140082 for ; Thu, 2 Apr 2015 20:56:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752353AbbDBJ4E (ORCPT ); Thu, 2 Apr 2015 05:56:04 -0400 Received: from mout.web.de ([212.227.15.4]:57315 "EHLO mout.web.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752347AbbDBJ4D (ORCPT ); Thu, 2 Apr 2015 05:56:03 -0400 Received: from kongar.lan.local ([185.44.151.123]) by smtp.web.de (mrweb004) with ESMTPSA (Nemesis) id 0LphiA-1Z7yrS2S98-00fUv3; Thu, 02 Apr 2015 11:55:56 +0200 From: Alexander Stein To: Jean-Christophe Plagniol-Villard , Linus Walleij Cc: Alexander Stein , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Ludovic Desroches Subject: [PATCH v3 1/1] pinctrl: at91: Add set_multiple GPIO chip feature Date: Thu, 2 Apr 2015 11:55:49 +0200 Message-Id: <1427968549-19837-1-git-send-email-alexanders83@web.de> X-Mailer: git-send-email 2.3.4 X-Provags-ID: V03:K0:dE/PdWGyjpd6Yzs4aLz+mIJthqXcme2kczNWIlKDaIhGJjsKqDw 2bpBTryzhPZ9sRsksB5E8kG6HUuWM8KDW05Eu6uzLrUprIAHIV4t28xL8dpN6yOMHh1/1pC v+ZUiYxJ0MRTJvRmaLktA+ppaLYAJay+xSLf5XMigD1FVPVR2OtrDeJqnlkh34HjlEdHa+a tm8scQY1g8vnQNFH2c4sg== X-UI-Out-Filterresults: notjunk:1; Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds the callback for set_multiple. As this controller has a separate set and clear register, we can't write directly to PIO_ODSR as this would required a cached variable and would race with at91_gpio_set. So build masks for the PIO_SODR and PIO_CODR registers and write them together. Signed-off-by: Alexander Stein --- I Just realized that some implementations have less than 32 pins. Thus BITS_MASK(chip->ngpio) as suggested by Jean-Christophe is actually required. I missed that, sorry for the noise. Changes in v3: * As not all GPIO controllers have 32 pins take ngpio into account Mask the set- and clear-mask to the supported GPIO pins Changes in v2: * Greatly simplyfied the implementation: Generate the set- and clear-mask directly from 'mask' and 'bits' drivers/pinctrl/pinctrl-at91.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index a4814066ea08..f1b0bfb94fcb 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1330,6 +1330,21 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); } +static void at91_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + +#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) + /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ + uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); + uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); + + writel_relaxed(set_mask, pio + PIO_SODR); + writel_relaxed(clear_mask, pio + PIO_CODR); +} + static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { @@ -1689,6 +1704,7 @@ static struct gpio_chip at91_gpio_template = { .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, .set = at91_gpio_set, + .set_multiple = at91_gpio_set_multiple, .dbg_show = at91_gpio_dbg_show, .can_sleep = false, .ngpio = MAX_NB_GPIO_PER_BANK,