From patchwork Mon Mar 23 12:18:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: grygorii.strashko@linaro.org X-Patchwork-Id: 453402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D5D9414010F for ; Mon, 23 Mar 2015 23:20:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752579AbbCWMTh (ORCPT ); Mon, 23 Mar 2015 08:19:37 -0400 Received: from mail-la0-f51.google.com ([209.85.215.51]:34659 "EHLO mail-la0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752398AbbCWMSl (ORCPT ); Mon, 23 Mar 2015 08:18:41 -0400 Received: by lagg8 with SMTP id g8so132496189lag.1 for ; Mon, 23 Mar 2015 05:18:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ttvvtm8r3f6YhTj03hTDXsNSG0kF4JsvdKHQZloQgvo=; b=CCcsuXa8T2Dd4+IfCHYYGAwAZ0uVdx58Lb7W9kMfDZDHm2Cgf/VW2yrBzSaGHb+QJY V9jkEfC5qwFHBdBwm/ANRX4JyeuYyU4kNYafEZJ3ekvqIu196pOxuBQV/t7ji17v11VL UCpyBilIIB0alPW430oeLDoeh520AVqVxB9S7zFGy7GJ/2Wj3P5ezIR56xL2prFOnkAV DV0TJXwnZXcXhfrySveCbheSsV4yRFWEiu9hteeGb9fc9zXmaFzozn8F9FXZ5P/bfzjV CRO9YVxPQhmB+G63nGwBm7VUTAPfRhHWCkdYN6cpZDrz6xYP9XfGPMBxU9Oc/QO3BV0O wkBQ== X-Gm-Message-State: ALoCoQni7DBpqTka/gmlCYnM0h4SKjmiWee1LKhz6vlXvclpu8s1NRVN7+e9KkeO3M9+7apKDdNo X-Received: by 10.112.167.4 with SMTP id zk4mr80670225lbb.74.1427113120054; Mon, 23 Mar 2015 05:18:40 -0700 (PDT) Received: from localhost ([195.238.92.128]) by mx.google.com with ESMTPSA id zz3sm154367lbb.5.2015.03.23.05.18.39 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 23 Mar 2015 05:18:39 -0700 (PDT) From: To: Javier Martinez Canillas , Linus Walleij , Alexandre Courbot , ssantosh@kernel.org, Kevin Hilman , tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Grygorii Strashko Subject: [PATCH v2 5/8] gpio: omap: convert gpio irq functions to use GPIO offset Date: Mon, 23 Mar 2015 14:18:27 +0200 Message-Id: <1427113110-20813-6-git-send-email-grygorii.strashko@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427113110-20813-1-git-send-email-grygorii.strashko@linaro.org> References: <1427113110-20813-1-git-send-email-grygorii.strashko@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Grygorii Strashko Convert GPIO IRQ functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO <-> GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain, so struct irq_data->hwirq contains GPIO offset This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Tested-by: Tony Lindgren Tested-by: Aaro Koskinen Acked-by: Santosh Shilimkar Acked-by: Javier Martinez Canillas Signed-off-by: Grygorii Strashko --- drivers/gpio/gpio-omap.c | 67 ++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index ff5d54d..628a132 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -549,9 +549,10 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) readl_relaxed(reg); } -static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) +static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, + unsigned offset) { - omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); + omap_clear_gpio_irqbank(bank, BIT(offset)); } static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) @@ -612,13 +613,13 @@ static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) writel_relaxed(l, reg); } -static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, - int enable) +static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, + unsigned offset, int enable) { if (enable) - omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); + omap_enable_gpio_irqbank(bank, BIT(offset)); else - omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); + omap_disable_gpio_irqbank(bank, BIT(offset)); } /* @@ -629,14 +630,16 @@ static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, * enabled. When system is suspended, only selected GPIO interrupts need * to have wake-up enabled. */ -static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) +static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, + int enable) { - u32 gpio_bit = GPIO_BIT(bank, gpio); + u32 gpio_bit = BIT(offset); unsigned long flags; if (bank->non_wakeup_gpios & gpio_bit) { dev_err(bank->dev, - "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); + "Unable to modify wakeup on non-wakeup GPIO%d\n", + offset); return -EINVAL; } @@ -652,22 +655,22 @@ static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) return 0; } -static void omap_reset_gpio(struct gpio_bank *bank, int gpio) +static void omap_reset_gpio(struct gpio_bank *bank, unsigned offset) { - omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); - omap_set_gpio_irqenable(bank, gpio, 0); - omap_clear_gpio_irqstatus(bank, gpio); - omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); - omap_clear_gpio_debounce(bank, GPIO_INDEX(bank, gpio)); + omap_set_gpio_direction(bank, offset, 1); + omap_set_gpio_irqenable(bank, offset, 0); + omap_clear_gpio_irqstatus(bank, offset); + omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); + omap_clear_gpio_debounce(bank, offset); } /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); + unsigned offset = d->hwirq; - return omap_set_gpio_wakeup(bank, gpio, enable); + return omap_set_gpio_wakeup(bank, offset, enable); } static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) @@ -705,7 +708,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) spin_lock_irqsave(&bank->lock, flags); bank->mod_usage &= ~(BIT(offset)); omap_disable_gpio_module(bank, offset); - omap_reset_gpio(bank, bank->chip.base + offset); + omap_reset_gpio(bank, offset); spin_unlock_irqrestore(&bank->lock, flags); /* @@ -819,14 +822,13 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d) static void omap_gpio_irq_shutdown(struct irq_data *d) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); unsigned long flags; - unsigned offset = GPIO_INDEX(bank, gpio); + unsigned offset = d->hwirq; spin_lock_irqsave(&bank->lock, flags); bank->irq_usage &= ~(BIT(offset)); omap_disable_gpio_module(bank, offset); - omap_reset_gpio(bank, gpio); + omap_reset_gpio(bank, offset); spin_unlock_irqrestore(&bank->lock, flags); /* @@ -840,43 +842,42 @@ static void omap_gpio_irq_shutdown(struct irq_data *d) static void omap_gpio_ack_irq(struct irq_data *d) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); + unsigned offset = d->hwirq; - omap_clear_gpio_irqstatus(bank, gpio); + omap_clear_gpio_irqstatus(bank, offset); } static void omap_gpio_mask_irq(struct irq_data *d) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); + unsigned offset = d->hwirq; unsigned long flags; spin_lock_irqsave(&bank->lock, flags); - omap_set_gpio_irqenable(bank, gpio, 0); - omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); + omap_set_gpio_irqenable(bank, offset, 0); + omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); spin_unlock_irqrestore(&bank->lock, flags); } static void omap_gpio_unmask_irq(struct irq_data *d) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); - unsigned int irq_mask = GPIO_BIT(bank, gpio); + unsigned offset = d->hwirq; u32 trigger = irqd_get_trigger_type(d); unsigned long flags; spin_lock_irqsave(&bank->lock, flags); if (trigger) - omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); + omap_set_gpio_triggering(bank, offset, trigger); /* For level-triggered GPIOs, the clearing must be done after * the HW source is cleared, thus after the handler has run */ - if (bank->level_mask & irq_mask) { - omap_set_gpio_irqenable(bank, gpio, 0); - omap_clear_gpio_irqstatus(bank, gpio); + if (bank->level_mask & BIT(offset)) { + omap_set_gpio_irqenable(bank, offset, 0); + omap_clear_gpio_irqstatus(bank, offset); } - omap_set_gpio_irqenable(bank, gpio, 1); + omap_set_gpio_irqenable(bank, offset, 1); spin_unlock_irqrestore(&bank->lock, flags); }