From patchwork Wed Mar 18 17:21:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 451554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 13CD214008F for ; Thu, 19 Mar 2015 04:22:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756586AbbCRRVd (ORCPT ); Wed, 18 Mar 2015 13:21:33 -0400 Received: from mail-wg0-f41.google.com ([74.125.82.41]:36304 "EHLO mail-wg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756510AbbCRRV2 (ORCPT ); Wed, 18 Mar 2015 13:21:28 -0400 Received: by wgra20 with SMTP id a20so41045183wgr.3 for ; Wed, 18 Mar 2015 10:21:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xShya5eFHyQ6msTZc6Ct1gSTNspysWowiPFGjGFcdeI=; b=gJULwe7pDd2IO5DiJvb3TPuqdEhwhwcN6fb5cdbBkfcubyEuB1XFDPMf2o4QjcjK4V OmybKvxmgcsdWCXO6yKxdU9kWDXtqKoS8lCw+Ty8fqHeuFDTSgATW5hcIL23XBk+QAGP dSudSSpE4ownfhGE4CiAQlivXxy8448ZkyXd5Be4vFJmTRjY8ALBfNRP/1s/M75owt85 /t6MDlgdsmF+fzFaJbzEi4vsNCrRJpDSpeDDCX6tHotJra+bkBR2lILJ0oNS/CrC3n/V 8sfobVBubxSA2/bepNXM2MRyHVCqELLF/asUAKtyCYm2llD88GEAxtgFAE8Df17BB/TZ xQGg== X-Gm-Message-State: ALoCoQkNZjViV1A08a2DkT0EdgbMJF5XNJn53uQ3L0u1yrqMb6oFFMvJPHibpoEHJjhTeGhs4ZqR X-Received: by 10.194.108.9 with SMTP id hg9mr146968189wjb.68.1426699286577; Wed, 18 Mar 2015 10:21:26 -0700 (PDT) Received: from localhost.localdomain ([81.134.86.251]) by mx.google.com with ESMTPSA id v13sm4021936wij.10.2015.03.18.10.21.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Mar 2015 10:21:25 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, Karim BEN BELGACEM Subject: [PATCH v2 1/6] ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35 Date: Wed, 18 Mar 2015 17:21:14 +0000 Message-Id: <1426699279-9258-2-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426699279-9258-1-git-send-email-lee.jones@linaro.org> References: <1426699279-9258-1-git-send-email-lee.jones@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Karim BEN BELGACEM This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM Acked-by: Maxime Coquelin Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 402844c..0a754f2 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -104,6 +104,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO5"; + st,retime-pin-mask = <0x3f>; }; rc { @@ -519,6 +520,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO35"; + st,retime-pin-mask = <0x7f>; }; i2c4 {